Abstract: Medical devices and methods are disclosed. An example method for accessing a body lumen may include providing a catheter system. The catheter system may include a catheter shaft having a lumen defined therein and an outer wall surface having a channel formed therein. A first guidewire may be disposed in the channel and a second guidewire may be disposed in the lumen. The method may also include advancing the catheter system through a body lumen to a location where the body lumen splits into a first section and a second section, advancing the first guidewire into the first section, and advancing the second guidewire into the second section, and advancing the catheter shaft along the second guidewire and into the second section. Advancing the catheter shaft along the second guidewire and into the second section may remove at least a portion of the first guidewire from the channel.

Abstract: Medical devices and methods are disclosed. An example method for accessing a body lumen may include providing a catheter system. The catheter system may include a catheter shaft having a lumen defined therein and an outer wall surface having a channel formed therein. A first guidewire may be disposed in the channel and a second guidewire may be disposed in the lumen. The method may also include advancing the catheter system through a body lumen to a location where the body lumen splits into a first section and a second section, advancing the first guidewire into the first section, and advancing the second guidewire into the second section, and advancing the catheter shaft along the second guidewire and into the second section. Advancing the catheter shaft along the second guidewire and into the second section may remove at least a portion of the first guidewire from the channel.

Abstract: A resource arbiter in a system with multiple shared resources and multiple requestors may implement an adaptive resource management approach that takes advantage of time-varying requirements for granting access to at least some of the shared resources. For example, due to pipelining, signal timing issues, or a lack of information, more resources than are required to perform a task may need to be available for allocation to a requestor before its request for the needed resources is granted. The requestor may request only the resources it needs, relying on the arbiter to determine whether additional resources are required in order to grant the request. The arbiter may park a high priority requestor on idle resources, thus allowing requests for those resources by the high priority requestor to be granted on the first clock cycle of a request. Other requests may not be granted until at least a second clock cycle.

Abstract: A resource arbiter in a system with multiple shared resources and multiple requestors may implement an adaptive resource management approach that takes advantage of time-varying requirements for granting access to at least some of the shared resources. For example, due to pipelining, signal timing issues, or a lack of information, more resources than are required to perform a task may need to be available for allocation to a requestor before its request for the needed resources is granted. The requestor may request only the resources it needs, relying on the arbiter to determine whether additional resources are required in order to grant the request. The arbiter may park a high priority requestor on idle resources, thus allowing requests for those resources by the high priority requestor to be granted on the first clock cycle of a request. Other requests may not be granted until at least a second clock cycle.

Abstract: Medical devices and methods are disclosed. An example method for accessing a body lumen may include providing a catheter system. The catheter system may include a catheter shaft having a lumen defined therein and an outer wall surface having a channel formed therein. A first guidewire may be disposed in the channel and a second guidewire may be disposed in the lumen. The method may also include advancing the catheter system through a body lumen to a location where the body lumen splits into a first section and a second section, advancing the first guidewire into the first section, and advancing the second guidewire into the second section, and advancing the catheter shaft along the second guidewire and into the second section. Advancing the catheter shaft along the second guidewire and into the second section may remove at least a portion of the first guidewire from the channel.

Abstract: Methods of testing a honeycomb filter include the step of wetting the outer peripheral surface of the honeycomb filter to enhance the flow of fog through outer peripheral channels of the honeycomb network of channels. In further examples, methods include the step of obstructing a flow of fog through inner peripheral channels to enhance the flow of fog through the outer peripheral channels of the honeycomb network of channels. In further examples, apparatus for testing a honeycomb filter include a flow diverter with a blocking member.

Abstract: Methods of testing a honeycomb filter include the step of wetting the outer peripheral surface of the honeycomb filter to enhance the flow of fog through outer peripheral channels of the honeycomb network of channels. In further examples, methods include the step of obstructing a flow of fog through inner peripheral channels to enhance the flow of fog through the outer peripheral channels of the honeycomb network of channels. In further examples, apparatus for testing a honeycomb filter include a flow diverter with a blocking member.

Abstract: An apparatus and method for manufacturing a honeycomb article with an after-applied skin, where the edges of the after-applied skin are relieved with respect to the ends of the honeycomb article.

Abstract: A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

Abstract: An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224, 226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

Abstract: A hand held dispenser of hot water intended for weed control purposes has a handle containing a hose connection, a flow regulator, a heating tube, an exit tube, a nozzle and a power switch. The handle is connected to a tube which contains a main electric water heating element surrounded by a tube through which water can flow form the bottom of the wand towards the handle before being piped through an exit tube to the nozzle. A temperature sensor is positioned adjacent the handle to regulate the power supplied to the heating element.

Abstract: A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

Abstract: A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

Abstract: An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

Abstract: A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

Abstract: A system (50) has a shifting delay circuit (60) which provides a variable delay for delaying a source clock and a delay locked loop (DLL) (70) which includes a delay line (72) which provides a variable delay for delaying the source clock. The delay line (18) has its delay varied by a counter (74). The counter (74) is incremented in order to change the delay. The shifting delay circuit (60) is based on half periods of a reference clock (GCLK) which has a known relationship to the source clock. The total delay for the source clock is a combination of that provided by shifting delay circuit (60) and delay line (72). The delay line (72), which requires relatively large amounts of die area in an integrated circuit can be smaller in size due to the usage of shifting delay circuit (60).

Abstract: A rotary drill bit, for drilling holes in subsurface formations, comprises a bit body, cutting structures mounted on the bit body, and a fluid supply system for supplying drilling fluid to the surface of the bit body, to cool and clean the cutting structures. The fluid supply system comprises a number of nozzles mounted in the bit body, a main passage in the bit body and a number of auxiliary passages leading from the main passage to the nozzles. Some or all of the passages are at least partly lined with an erosion-resistant lining material. The lining material may comprise a hard facing applied to the internal surface of a preformed passage or a rigid tube which itself defines the internal surface of the passage.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. The CPUs are structured to operate in one of two modes: a simplex mode in which the two CPUs operate independently of each other, and a duplex mode in which the CPUs operate in lock-step synchronism to execute each instruction of identical instruction streams at substantially the same time. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system.

Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.