Abstract: A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.

Abstract: A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.

Abstract: A plurality of transaction domains include transaction managers owning respective transactions, where a first of the transactions is uniquely identified by a unique identifier that indicates a first of the transaction managers that owns the first transaction, the unique identifier relating to the transaction domain in which the first transaction manager is included. The first transaction manager receives a request from a requester that initiated the first transaction, the request sent to the first transaction manager based on the unique identifier of the first transaction.

Abstract: A display apparatus includes an array of light modulators. Each light modulator has a first actuator configured to drive the light modulator into a first state and a second actuator configured to drive the light modulator into a second state. The display apparatus also includes a control matrix including, for each light modulator in the array, a single actuation voltage interconnect. The actuation voltage interconnect is configured to apply a first drive voltage to the first actuator of the light modulator and apply a second drive voltage to the second actuator of the light modulator. In addition, the actuation voltage interconnect is configured to control application of a data voltage to a latch circuit to control the application of the first and second drive voltages to the first and second actuators.

Abstract: In one general aspect, a stream-based memory circuit is disclosed that includes physical storage elements and at least a first physical access port. A stream-based access controller is operatively connected to the physical storage elements and to the access port. The controller includes function-specific hardware logic operative to access data as streams in the physical memory in response to stream-based access commands at the access port.

Abstract: In one general aspect, a stream-based memory circuit is disclosed that includes physical storage elements and at least a first physical access port. A stream-based access controller is operatively connected to the physical storage elements and to the access port. The controller includes function-specific hardware logic operative to access data as streams in the physical memory in response to stream-based access commands at the access port.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.

Abstract: An encoding system uses a modified 8/9 rate modulation code to encode 8-bit data symbols into 9-bit cells in a conventional manner in accordance with the modified code and 9-bit ECC symbols into 10-bit cells by (i) encoding 8 bits of the symbol into a 9-bit cell in accordance with the modified code, and (ii) inserting into the 9-bit cell the remaining, that is, the non-encoded, bit of the ECC symbol. The system reproduces the 8-bit data symbols by decoding the 9-bit cells in a conventional manner in accordance with the modified code, and the 9-bit ECC symbols by (i) removing from the associated 10-bit cell the bit inserted during encoding, (ii) decoding the remaining 9 bits to reproduce 8 bits of the symbol, and (iii) inserting into the 8 bits the bit that was earlier removed. In an exemplary embodiment, the 8 least significant bits of the ECC symbol are encoded using the modified 8/9 rate code. The 9 bits produced by the code are used essentially as the first "c" bits and last "10-c" bits of a 10-bit cell.