Abstract: An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means (1010) compute for a next iteration symbol messages ??m from a representation of a corresponding symbol value stored in a first memory 1005 and from check node messages ?mn from a previous iteration. A shuffler (1030) changes a sequence of the symbol message received from the first computation means (1010) in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (1015). Third computation means (1020) update the representation of the symbol values in the first memory in dependence on output of the first and second computing means.

Abstract: An electronic device is provided which comprises a barrel shifter unit (BS) for performing a rotation of an input. The barrel shifter unit comprises a first and second barrel shifter (BS1, BS2). The electronic device furthermore comprises a selection unit for selecting a first set of elements (a) for the second barrel shifter (BS2) and a second set of elements for the first barrel shifter (BS1). The electronic device furthermore comprises a plurality of second multiplexers (M1 M8) for receiving the input of the second barrel shifter as first input and the output of the first barrel shifter as second input.

Abstract: An integrated circuit includes functional blocks and a data communication network having network stations interconnected via communication channels for communicating data packages between the functional blocks. Each data package includes N data elements having a data element with routing information for the network stations, N being an integer of at least two. The network stations include data routers and network interfaces, where each of the data routers is coupled to a functional block via a network interface. The data communication network includes first and second network stations interconnected through a first communication channel. The network includes M*N data storage elements, M being a positive integer, for introducing a delay of M*N cycles on the first communication channel.

Abstract: An integrated circuit comprises a plurality of data processing circuits (10) and a communication network (12) coupled between the data processing circuits (10). The communication network (12) comprises connections (122) and router circuits (120) coupled between the connections (122). Memory is provided to store definitions for respective data streams, of respective paths along the connections (122), for controlling the router circuits (120) to transmit each data item from each respective data stream along the respective path programmed for that respective data stream. Initially initial paths for a set of original data streams are defined and started. Subsequently an additional data stream can be added. If so a new path is selected in combination with future paths for the original data streams.

Abstract: An electronic device is provided which comprises a barrel shifter unit (BS) for performing a rotation of an input. The barrel shifter unit comprises a first and second barrel shifter (BS1, BS2). The electronic device furthermore comprises a selection unit for selecting a first set of elements (a) for the second barrel shifter (BS2) and a second set of elements for the first barrel shifter (BS1). The electronic device furthermore comprises a plurality of second multiplexers (M1 M8) for receiving the input of the second barrel shifter as first input and the output of the first barrel shifter as second input.

Abstract: An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IP1-IP5) to enable a communication between the processing modules (IP1-IP5). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IP1-IP5). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (T0-T4) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (T0-T4) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (T0-T4).

Abstract: An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means (1010) compute for a next iteration symbol messages ??m from a representation of a corresponding symbol value stored in a first memory 1005 and from check node messages ?mn from a previous iteration. A shuffler (1030) changes a sequence of the symbol message received from the first computation means (1010) in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation N means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (1015). Third computation means (1020) update the representation of the symbol values in the first memory in dependence on output of the first and second computing means.

Abstract: An integrated circuit comprises a plurality of data processing circuits (10) and a communication network (12) coupled between the data processing circuits (10). The communication network (12) comprises connections (122) and router circuits (120) coupled between the connections (122). Memory is provided to store definitions for respective data streams, of respective paths along the connections (122), for controlling the router circuits (120) to transmit each data item from each respective data stream along the respective path programmed for that respective data stream. Initially initial paths for a set of original data streams are defined and started. Subsequently an additional data stream can be added. If so a new path is selected in combination with future paths for the original data streams.

Abstract: An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IP1-IP5) to enable a communication between the processing modules (IP1-IP5). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IP1-IP5). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (TO-T4) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (TO-T4) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (TO-T4).

Abstract: An electronic device is provided comprising a plurality of first shared resources (SR1-SR4) and a plurality of arbiter units (AAU1-AAU4) each for performing an arbitration for at least one of the plurality of shared resources (SR1-SR4). The communication between the arbiter units (AAU1-AAU4) is performed on an asynchronous basis, and the data communication between the first shared resources is performed on an asynchronous basis. Each arbiter unit (AAU1-AAU4) is adapted for sending a first token (T) to at least one neighboring arbiter unit (AAU1-AAU4), and for receiving a second token (T) from at least one neighboring arbiter unit (AAU1-AAU4) to implement a first global notion of time.

Abstract: An integrated circuit (10) comprises a plurality of functional blocks (101, 102, 103, 104) and a data communication network (100) comprising a plurality of network stations being interconnected via a plurality of communication channels (150) for communicating data packages between the functional blocks (101, 102, 103, 104). Each data package comprising N data elements including a data element comprising routing information for the network stations (110, 120, 130, 140), N being an integer of at least two.

Abstract: The invention relates to a method for allocating data to at least one packet in an integrated circuit, the integrated circuit comprising a network through which the packet is sent from a first module to at least one second module, the method comprising the step of determining the length of the packet. The length of a packet is determined on basis of dynamically known parameters instead of statically known parameters, which increases flexibility with regard to the allocation of data units to packets. The method of packetization takes into account runtime aspects when determining the length of the packets to be transmitted via the communication channels of the network.

Abstract: The present invention relates to an integrated circuit comprising a plurality of processing modules (M, S) and an interconnect means (N) for coupling said plurality of processing modules (M, S) and for enabling a packet based communication based on transactions between said plurality of processing modules (M, S). Each packet comprises a number of subsequent words. A first of said plurality of processing modules (M) issues a transaction by sending a plurality of messages (msg1, msg2) over said interconnect means (N) to a second of said plurality of processing modules (S). At least one packet inspecting unit (PIU) is provided for packetizing said plurality of messages (msg1, msg2) into a plurality of packets and for inspecting said packets in order to determine unused space in said packets and to fill up said unused space with data from at least one subsequent message (msg1, msg2).