Patents by Inventor John Dischiano

John Dischiano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and device for supporting flip chip circuitry in analysis
    Patent number: 6448801
    Abstract: A method and structure are provided for an effective and efficient method and device for supporting a flip chip die undergoing analysis. The method and device provide added support and rigidity to flip chip dies. The method and device can facilitate multiple rounds of circuit testing and debugging. The result of the method and device is durable casing for flip chip device analysis.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Dischiano
  • Arrangement for accessing region of a flip chip die
    Patent number: 6448662
    Abstract: A method and structure for accessing the circuit region on a flip chip die are provided. The method and device permit multiple portions of the circuit region to be tested and analyzed simultaneously or in sequence. Access to the circuit region is gained without deteriorating any portions of the circuit region through the process. In a similar fashion, the new method and device allow for the circuit region to be efficiently modified, or “debugged,” and then returned into operation.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: September 10, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Dischiano
  • Alternate method and device for analysis of flip chip electrical connections
    Patent number: 6368188
    Abstract: An alternative method and device for accessing the circuit region on a flip chip die are provided. The new method and device provide increased accuracy for accessing the electrical contacts within the circuit region. Such a method and device is necessary in order to analyze and resolve flaws among the electrical contacts between a flip chip die and the chip package. The new method and device is precise enough to avoid adding defects upon approach to the contact intended for analysis. Specific regions of the electrical contact can be isolated for study. The technique is equally efficient for mass fabrication design testing and analysis.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: April 9, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Dischiano
  • METHOD AND DEVICE FOR SUPPORTING FLIP CHIP CIRCUITRY IN ANALYSIS
    Publication number: 20020003431
    Abstract: A method and structure are provided for an effective and efficient method and device for supporting a flip chip die undergoing analysis. The method and device provide added support and rigidity to flip chip dies. The method and device can facilitate multiple rounds of circuit testing and debugging. The result of the method and device is durable casing for flip chip device analysis.
    Type: Application
    Filed: June 5, 1998
    Publication date: January 10, 2002
    Applicant: Advanced Micro Devices, Inc.
    Inventor: JOHN DISCHIANO
  • Device for removing a flip chip die from packaging
    Patent number: 6239481
    Abstract: A method and structure for accessing the circuit region on a flip chip die are provided. The method and device permit multiple portions of the circuit region to be tested and analyzed simultaneously or in sequence. Access to the circuit region is gained without deteriorating any portions of the circuit region through the process. In a similar fashion, the new method and device allow for the circuit region to be efficiently modified, or “debugged,” and then returned into operation.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: May 29, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Dischiano
  • Method and device for positioning and accessing a die under analysis
    Patent number: 6139403
    Abstract: A method and device which is provided for thinning flip chip bonded integrated circuit (IC) devices with better accuracy. The method and device permit a successful approach to one portion of the circuit while leaving other portions of the circuit intact. Thus, other portions of the circuit can be the subject of later analysis or can be modified as debugging may require. The method and device provide the above stated capability in an effective and efficient manner.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: October 31, 2000
    Assignee: Advanced Micro Devices
    Inventor: John Dischiano
  • Method and device for analysis of flip chip electrical connections
    Patent number: 6106367
    Abstract: An alternative method and device for accessing the circuit region on a flip chip die are provided. The new method and device provide increased accuracy for accessing the electrical contacts within the circuit region. Such a method and device is necessary in order to analyze and resolve flaws among the electrical contacts between a flip chip die and the chip package. The new method and device is precise enough to avoid adding defects upon approach to the contact intended for analysis. Specific regions of the electrical contact can be isolated for study. The technique is equally efficient for mass fabrication design testing and analysis.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: August 22, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: John Dischiano