Abstract: A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

Abstract: A memory controller comprises a system bus interface that connects the MC to a system processor, a system memory interface that connects the MC to a system memory, a read buffer comprising a plurality of entries constituting storage areas, the entries comprising at least one read buffer entry (RBE) and at least one extended prefetch read buffer entry (EPRBE), read buffer logic, dynamic controls that are used by the read buffer logic, and an MC processor comprising at least one extended prefetch machine (EPM), each corresponding to one of the at least EPRBEs, where the MC processor is configured to allocate and deallocate EPRBEs and RBEs according to an allocation method using the dynamic controls.

Abstract: A data processing system includes a plurality of processing units and a system memory coupled to a memory controller. The system memory includes a persistent memory device and a non-persistent cache interposed between the memory controller and the persistent memory device. The memory controller receives a flush request of a particular processing unit among the plurality of processing units, the flush request specifying a target address. The memory controller, responsive to the flush request, ensures flushing of a target cache line of data identified by target address from the non-persistent cache into the persistent memory device.

Abstract: A data processing system includes a plurality of processing units and a system memory coupled to a memory controller. The system memory includes a persistent memory device and a non-persistent cache interposed between the memory controller and the persistent memory device. The memory controller receives a flush request of a particular processing unit among the plurality of processing units, the flush request specifying a target address. The memory controller, responsive to the flush request, ensures flushing of a target cache line of data identified by target address from the non-persistent cache into the persistent memory device.

Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., a synchronization bit or bits) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A technique for memory command throttling in a partitioned memory subsystem includes accepting, by a master memory controller included in multiple memory controllers, a synchronization command. The synchronization command includes command data that includes an associated synchronization indication (e.g., synchronization bit(s)) for each of the multiple memory controllers and each of the multiple memory controllers controls a respective partition of the partitioned memory subsystem. In response to receiving the synchronization command, the master memory controller forwards the synchronization command to the multiple memory controllers. In response to receiving the forwarded synchronization command each of the multiple memory controllers de-asserts an associated status bit. In response to receiving the forwarded synchronization command, each of the multiple memory controllers determines whether the associated synchronization indication is asserted.

Abstract: A system and method for managing data is provided. The system includes a network for interconnecting a plurality of computers. A data storage means is connected to the network to receive, store and transmit a plurality of files to and from the network. A plurality of computers is also connected to the network. Each computer is configured for originating and for receiving files. Each of the files has a unique identifier associated therewith. Each computer may retrieve a file from the data storage means using the unique identifier.

Abstract: A computer implemented method for managing an information handling system. The method may include one or more of: monitoring, with an object oriented model, the information handling system for an event; generating, with the object oriented model, an indication in response to the event; and/or allowing access to the indication to clients having a sufficient client level of access.

Abstract: A computer implemented method for managing an information handling system. The method may include one or more of: monitoring, with an object oriented model, the information handling system for an event; generating, with the object oriented model, an indication in response to the event; and/or allowing access to the indication to clients having a sufficient client level of access.

Abstract: A computer-implemented method for instantiating an object of an object oriented model. The method may include receiving communication from a provider to instantiate the object. The method may also include determining if the provider is a first provider to instantiate the object If the provider is the first provider, the method may also include receiving communication whether the object is to be designated as a shared object or private object, and then designating the object as communicated by the provider.

Abstract: A system and method for previewing a disk drive's disk data format (DDF) metadata before performing an “import” or “clear” method to make it available on a receiving system comprising a redundant array of independent disks (RAID) array. A preview method is implemented such that the DDF metadata of one or more disk drives comprising a foreign configuration can be examined prior to importing or clearing the disk. New objects are derived from existing virtual disk and physical disk array objects that have the same characteristics as existing object definitions. These new objects are aggregated to comprise a new foreign configuration object when foreign metadata is discovered on a drive by a receiving RAID controller.

Abstract: A globalization component including a base class NewResourceManager that provides a layer of abstraction from the Microsoft Resource Manager and a new WinForm class that inherits from the .NET Windows Form and utilizes NewResourceManager. The globalization component uses culture information and resource folder information from the registry to set a culture-specific resource folder and file. Decoupled assembly culture-specific resource files include all string resources in the target language and can be stored in any folder. New culture-specific resource files are easily generated without having to recompile the assembly or any satellite assemblies and without having to modify any configuration files. The NewWinForm class can also iterate through all controls on the form and if values are missing from an associated resource file, the resource manager will save the missing controls to a text file. Translators need only receive this text file to translate from one human language to another.

Abstract: A method, apparatus and computer instructions are disclosed for seamlessly transporting a language-independent message (e.g., embedded NLS emblems) encoded from a source code at a layer below a management framework, through the management framework, and on to a client layer for consumption by a user. Consequently, for example, the process of displaying an error condition message to a client can be decoupled completely from the point where the error occurred, but the details and context of the error can still be preserved. As such, a generic solution is disclosed that is independent of the NLS language and locale and particular management framework involved. Advantageously, for example, a system programmer can write a significant amount of a system's messaging code independently of the management framework involved.

Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

Abstract: A data processing system having a physically addressed cache of disk memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space that is equal to the virtual address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Abstract: A method, apparatus, and computer instructions for providing addresses to clients. A request is received from a client for an address. A determination is made as to whether authentication information is present in the request. A verification process is performed using the authentication information if the authentication information is presenting the request. A determination is made as to whether the authentication information is authenticated. A privileged address is provided to the client in response to the authentication information being authenticated.