Abstract: A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB).

Abstract: A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB).

Abstract: A CMOS output stage is disclosed. The CMOS output stage comprises a substrate and at least one well coupled to the substrate. The CMOS output stage also includes a plurality of slots provided through the one well into the substrate. Each of the slots are oxidized. Each of the plurality of slots are filled with metal to provide a plurality of power busses. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector. This results in the buried power buss metal always having oxide isolated surroundings. This feature allows all of these power busses to be established wherever necessary without causing any circuit issues since they are always insulated from other areas of the device. One of the power busses provides a ground. One of the power busses provides an output. One of the power busses provides a power connector.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 um deep and 5 to 6 um wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing.

Abstract: A method and system for providing a power enhanced lateral DMOS device is disclosed. The method and system comprise providing a semiconductor substrate with a plurality of source/body structures thereon. The method and system further comprise providing a slot in the semiconductor substrate between the plurality of source/body structures to provide a truncated source; and providing a metal within the slot to provide a ground strap device.

Abstract: A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system includes providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the substrate region. Finally, the method and system includes oxidizing the slot except at the bottom of the slot and providing a metal within the slot.

Abstract: An integrated Schottky diode and method of manufacture of such a diode is disclosed. In a first aspect, a Schottky diode comprises a semiconductor substrate. The semiconductor substrate includes an epitaxial layer (EPI) on the substrate region. The diode includes a plurality of guard rings in the EPI layer and a plurality of oxidized slots. Finally, the diode includes metal within the plurality of slots to form a Buried Power Buss. A portion of the metal is completely oxide isolated from the other elements of the diode. In a second aspect, a method for manufacturing a Schottky diode comprises providing a substrate region, A buried N+ region providing an epitaxial (EPI) layer. The method also includes providing a plurality of guard rings in the EPI layer and providing a plurality of slots in the semiconductor substrate that is in contact with the EPI layer and the substrate region.

Abstract: A method and system for providing a sinker on a semiconductor device is described. The method and system includes providing a substrate region and providing a buried layer and an epitaxial (EPI) layer over the substrate region. The method and system further includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the buried layer and the substrate region. The method and system finally includes oxidizing the slot except at the bottom of the slot and providing metal within the slot.

Abstract: A method and system for providing a bipolar power transistor on a semiconductor device is disclosed. The method and system comprise providing a semiconductor substrate. The method and system includes providing an emitter base structure in the power device. The method and system further includes providing at least one oxidized slot through the emitter base structure and into the semiconductor substrate utilizing the highly inefficient portion of the emitter for this structure, thus wasted space is utilized to provide a power buss ground. This results in a smaller transistor for a given current. This is provided without any extra steps. This approach results in lower operating temperatures for a given current as compared to standard approaches.

Abstract: A method and system for providing a ground strap on a semiconductor device is disclosed. The method and system comprises providing a substrate region and providing an epitaxial (EPI) layer over the substrate region. The method and system includes etching a plurality of device structures in the EPI layer and providing a slot in the semiconductor substrate that is in contact with the substrate region. Finally, the method and system includes oxidizing the slot except at the bottom of the slot and providing a metal within the slot.

Abstract: A method and system for providing a power enhanced lateral DMOS device is disclosed. The method system comprise providing a semiconductor substrate with a plurality of source/body structures thereon. The method and system further comprise providing a slot in the semiconductor substrate between the plurality of source/body structures to provide a truncated source; and providing a metal within the slot to provide a ground strap device.

Abstract: A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer, an emitter region between the first and second collector regions. Therefore slots are placed in each of the regions. Accordingly, in a first approach the standard process flow will be followed until reaching the point where contact openings and metal are to be processed. In this approach slots are etched that are preferably 5 to 6 &mgr;m deep and 5 to 6 &mgr;wide. These slots are then oxidized and will be subsequently metalized. When used for making metal contacts to the buried layer or for ground the oxide is removed from the bottom of the slots by an anisotropic etch. Subsequently when these slots receive metal they will provide contacts to the buried layer where this is desired and to the substrate when a ground is desired. In a second approach the above-identified process is completed up through the slot process without processing the lateral PNPs.

Abstract: A method and system for providing a power enhanced lateral DMOS device is disclosed. The method and system comprise providing a semiconductor substrate with a plurality of source/body structures thereon. The method and system further comprise providing a slot in the semiconductor substrate between the plurality of source/body structures to provide a truncated source; and providing a metal within the slot to provide a ground strap device.

Abstract: A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In addition, the process described in the present invention provides additional advantages that the ASSET process does not have.

Abstract: The present invention provides a unique methodology for device and process technology that results in significant improvements in the parameters of the active devices of all integrated technologies including: bipolar, CMOS, BiCmos, BCD (Bipolar, Cmos, DMOS), and DMOS. The approach results in fewer process steps than the standard approach in each of these technologies, while providing lower capacitance, higher speed, lower power dissipation, lower Ron, lower ground resistance, lower output resistance, reduced de-biasing at high current, higher breakdown voltage, higher beta and over a broader current range while providing significant reduction in die size. Use of this approach also results in improved Schottky diodes and solar cells.