Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: A stacked block array architecture.for a SRAM memory for low power applications. The architecture turns on only the required data cells and sensing circuitry to access a particular set of data cells of interest. The wordline delay is reduced by using a shorter and wider wordline wire size. Although less power is consumed, the performance is improved by the reduction in loading of wordlines and bitlines.

Abstract: A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.

Abstract: A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to the local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.

Abstract: A device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

Abstract: A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

Abstract: According to the present invention, a device and method is provided for reducing power consumption in memory devices. The present invention reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment of the present invention, the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

Abstract: According to the preferred embodiment, a device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment, the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.

Abstract: A memory cell responsive to a write enable signal for storing write signals present on a pair of write bit lines and responsive to a read enable signal for presenting stored data on a pair of read sense lines further includes a timed, active write load. The memory cell includes first and second NPN bipolar transistors having commonly connected emitters, and cross-coupled bases and collectors; and first and second PNP bipolar transistors configured as loads for the pair of NPN bipolar transistors. Write transistors are provided responsive to the write enable signal for draining current from a selected one of the first or second nodes. Transistors connected as diodes between the PNP bases and each of the cross-coupled NPN nodes are responsive to the current draining effected by the write transistors for biasing both of the first and second PNP transistors into an active mode of operation.

Abstract: A directory memory system including a plurality of reconfigurable subarrays of memory cells and having the capability of simultaneously performing write/compare, read/compare, compare/bypass, write/bypass, or write/compare/bypass operations. The present system may be fabricated on a single integrated circuit chip and includes circuitry for selectively writing data into the subarrays. Output data from the subarrays is connected to compare data logic for comparing the subarray data to one or more bytes of compare input data, and to bit select logic for selectively placing the subarray data onto an output bus. Bypass select logic causes either the subarray data or one byte of compare data to be output from the memory system data output port. In one embodiment, two bytes of compare input data can be simultaneously compared with a selected data byte from each of the subarrays, and one byte of compare input data can be bypassed to the data output port during the compare operation.

Abstract: A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.