Patents by Inventor John E. Barwin
John E. Barwin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9104832Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.Type: GrantFiled: January 22, 2014Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: John E. Barwin, III, Jason Chung, Amol A. Joshi, William J. Livingstone, Leon J. Sigal, Brian Worth, Paul S. Zuchowski
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Publication number: 20150205906Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.Type: ApplicationFiled: January 22, 2014Publication date: July 23, 2015Applicant: International Buiness Machines CorporationInventors: John E. Barwin, III, Jason Chung, Amol A. Joshi, William J. Livingstone, Leon J. Sigal, Brian Worth, Paul S. Zuchowski
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Patent number: 8938701Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit.Type: GrantFiled: August 14, 2013Date of Patent: January 20, 2015Assignee: International Business Machines CorporationInventors: John E. Barwin, Jeanne P. S. Bickford
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Patent number: 8656325Abstract: Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.Type: GrantFiled: January 12, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: John E. Barwin, Amol A. Joshi, Baozhen Li, Michael R. Ouellette
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Publication number: 20130332895Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: International Business Machines CorporationInventors: John E. BARWIN, Jeanne S. BICKFORD
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Patent number: 8560990Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.Type: GrantFiled: January 13, 2010Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: John E. Barwin, Jeanne P. S. Bickford
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Publication number: 20130185684Abstract: Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.Type: ApplicationFiled: January 12, 2012Publication date: July 18, 2013Applicant: International Business Machines CorporationInventors: John E. Barwin, Amol A. Joshi, Baozhen Li, Michael R. Ouellette
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Publication number: 20110173583Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.Type: ApplicationFiled: January 13, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. BARWIN, Jeanne P. S. BICKFORD
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Publication number: 20110107291Abstract: Disclosed are embodiments that allow for compensation of regional timing variations during timing analysis and, optionally, allow for optimize placement of critical paths, as a function of such regional timing variations. Based on an initial placement of devices for an integrated circuit chip, regional variations in one or more physical conditions that impact device timing (e.g., polysilicon perimeter density, average distance of devices to a well edge, average reflectivity) are mapped. Then, using a table that associates different derating factors with different levels of the physical condition(s), derating factors are assigned to different regions on the map. Next, a timing analysis is performed such that, for each region, delay of any path within that region is derated by the assigned derating factor. The map information can also be used when establishing a final placement of the devices on the integrated circuit chip in order to optimize placement of critical paths.Type: ApplicationFiled: November 5, 2009Publication date: May 5, 2011Applicant: International Business Machines CorporationInventors: John E. Barwin, Nazmul Habib, Manikandan Viswanath
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Publication number: 20090153228Abstract: Disclosed is a design structure of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.Type: ApplicationFiled: December 18, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John E. Barwin, Steven H. Lamphier, Harold Pilo
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Patent number: 7492199Abstract: The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.Type: GrantFiled: July 28, 2006Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: John E. Barwin, Harold Pilo
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Publication number: 20080265982Abstract: Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.Type: ApplicationFiled: June 6, 2008Publication date: October 30, 2008Applicant: International Business Machines CorporationInventors: John E. Barwin, Steven H. Lamphier, Harold Pilo
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Patent number: 7403061Abstract: Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.Type: GrantFiled: March 23, 2006Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: John E. Barwin, Steven H. Lamphier, Harold Pilo
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Publication number: 20080025447Abstract: The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.Type: ApplicationFiled: July 28, 2006Publication date: January 31, 2008Inventors: John E. Barwin, Harold Pilo
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Patent number: 7057924Abstract: The write path of an MRAM device is precharged before starting a write operation of a magnetic memory cell, increasing the speed of the write operation and decreasing the write cycle time. The reference wires are precharged, which provides better control over the wordline and bitline write pulses and results in shorter rise times. The precharge time can be hidden in the address decoding time or redundancy evaluation time. A circuit design for a global reference current generator is also described herein. A fast on circuit is also disclosed that increases the speed of precharging the reference wires.Type: GrantFiled: January 15, 2004Date of Patent: June 6, 2006Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Stefan Lammers, Hans-Heinrich Viehmann, Thomas M. Maffitt, John E. Barwin