Patents by Inventor John E. Barwin, III

John E. Barwin, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design
    Patent number: 9104832
    Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: John E. Barwin, III, Jason Chung, Amol A. Joshi, William J. Livingstone, Leon J. Sigal, Brian Worth, Paul S. Zuchowski
  • IDENTIFYING AND MITIGATING ELECTROMIGRATION FAILURES IN SIGNAL NETS OF AN INTEGRATED CIRCUIT CHIP DESIGN
    Publication number: 20150205906
    Abstract: A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 23, 2015
    Applicant: International Buiness Machines Corporation
    Inventors: John E. Barwin, III, Jason Chung, Amol A. Joshi, William J. Livingstone, Leon J. Sigal, Brian Worth, Paul S. Zuchowski