Patents by Inventor John E. Bertsch

John E. Bertsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6934671
    Abstract: A method of performing model to hardware correlation that simulates models based upon design criteria and manufactures devices based upon the design criteria. The method evaluates features of the devices during the manufacturing to produce in-line test parametric data, compares the models to the in-line test parametric data to obtain correlation data, and modifies the simulating according to the correlation data.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: John E. Bertsch, Daniel S. Coops, David M. Fried
  • Publication number: 20020193892
    Abstract: A method of performing model to hardware correlation that simulates models based upon design criteria and manufactures devices based upon the design criteria. The method evaluates features of the devices during the manufacturing to produce in-line test parametric data, compares the models to the in-line test parametric data to obtain correlation data, and modifies the simulating according to the correlation data.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 19, 2002
    Applicant: International Business Machines Corporation
    Inventors: John E. Bertsch, Daniel S. Coops, David M. Fried
  • Patent number: 5485095
    Abstract: Test circuits and methods for accurately flagging out-of-spec resistance in a current carrying structure of an integrated circuit employ a plurality of monitor structures connected in parallel and a test means for monitoring the monitor structures. Each monitor structure includes a test structure and an associated threshold sensitive device. Each test structure is predesigned relative to the current carrying structure of the integrated circuit such that an out-of-spec resistance in the test structure signals a possible out-of-spec resistance in the current carrying structure. The threshold sensitive device of each monitor structure outputs a fail signal when resistance of the associated test structure is above a predefined level. The fail signal is representative of an out-of-spec resistance in the associated test structure and flags possible out-of-spec resistance in the current carrying structure. The test means simultaneously monitors the plurality of monitor structures for a fail signal.
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: January 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: John E. Bertsch, Randy W. Mann, Edward J. Nowak, Minh H. Tong
  • Patent number: 4707667
    Abstract: An amplifier circuit having offset voltage and offset voltage drift corrections which does not require resistive feedback and is suitable for use with unmatched high frequency field effect transistor circuits. The described circuit cancels the offset voltage of a signal amplifier and comprises means for applying differential voltages to an operational amplifier, together with a switchable feedback connecting the output of the amplifier to one of its inputs and a capacitor coupled between the feedback input of the amplifier, and one of the differential voltages. This allows amplifying of low level AC signals while reducing the error introduced by the offset voltage or the offset voltage drift of the amplifier.
    Type: Grant
    Filed: April 30, 1986
    Date of Patent: November 17, 1987
    Assignee: International Business Machines Corporation
    Inventor: John E. Bertsch