Abstract: A photonic integrated circuit (PIC) is described. This PIC includes a semiconductor-barrier layer-semiconductor diode in an optical waveguide that conveys an optical signal, where the barrier layer is an oxide or a high-k material. Moreover, semiconductor layers in the semiconductor-barrier layer-semiconductor diode may include geometric features (such as a periodic pattern of holes or trenches) that create a lattice-shifted photonic crystal optical waveguide having a group velocity of light that is lower than the group velocity of light in the first semiconductor layer and the second semiconductor layer without the geometric features. The optical waveguide is included in an optical modulator, such as a Mach-Zehnder interferometer (MZI).

Abstract: A hybrid optical source that provides an optical signal having a wavelength is described. This hybrid optical source includes an edge-coupled optical amplifier (such as a III-V semiconductor optical amplifier) aligned to a semiconductor reflector (such as an etched silicon mirror). The semiconductor reflector efficiently couples (i.e., with low optical loss) light out of the optical amplifier in a direction approximately perpendicular to a plane of the optical amplifier. A corresponding optical coupler (such as a diffraction grating or a mirror) fabricated on a silicon-on-insulator chip efficiently couples the light into a sub-micron silicon-on-insulator optical waveguide. The silicon-on-insulator optical waveguide couples the light to additional photonic elements (including a reflector) to complete the hybrid optical source.

Abstract: A chip package includes a processor, an interposer chip and a voltage regulator module (VRM). The interposer chip is electrically coupled to the processor by first electrical connectors proximate to a surface of the interposer chip. Moreover, the interposer chip includes second electrical connectors proximate to another surface of the interposer chip, which are electrically coupled to the first electrical connectors by through-substrate vias (TSVs) in the interposer chip. Note that the second electrical connectors can electrically couple the interposer chip to a circuit board. Furthermore, the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop. For example, the VRM may be electrically coupled to the surface of the interposer chip, and may be adjacent to the processor. Alternatively, the VRM may be electrically coupled to the other surface of the interposer chip.

Abstract: A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit includes high-speed I/O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: An optical device with high thermal tuning efficiency is described. This optical device may be implemented using a tri-layer structure (silicon-on-insulator technology), including: a substrate, a buried-oxide layer and a semiconductor layer. In particular, a thermally tunable optical waveguide may be defined in the semiconductor layer. Furthermore, a portion of the substrate under the buried-oxide layer and substantially beneath a location of the thermally tunable optical waveguide is fabricated so that a portion of the buried-oxide layer is exposed. In this way, the thermal impedance between the thermally tunable optical waveguide and an external environment is increased, and power consumption associated with thermal tuning of the optical waveguide is reduced.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Abstract: A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

Abstract: A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates.

Abstract: An integrated circuit includes an optical source that provides an optical signal to an optical waveguide. In particular, the optical source may be implemented by fusion-bonding a III-V semiconductor to a semiconductor layer in the integrated circuit. In conjunction with surrounding mirrors (at least one of which is other than a distributed Bragg reflector), this structure may provide a cavity with suitable optical gain at a wavelength in the optical signal along a vertical direction that is perpendicular to a plane of the semiconductor layer. For example, the optical source may include a vertical-cavity surface-emitting laser (VCSEL). Moreover, the optical waveguide, defined in the semiconductor layer, may be separated from the optical source by a horizontal gap in the plane of the semiconductor layer. During operation of the optical source, the optical signal may be optically coupled across the gap from the optical source to the optical waveguide.

Abstract: A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.

Abstract: A chip package is described. This chip package includes a housing having a surface and a cavity, defined by an edge in the surface, with slots arranged at an angle relative to the surface. For example, the angle may be between 0° (in a plane of the surface) and 90° (perpendicular to the plane). Alternatively, the angle may be 0°. Moreover, the slots may be configured to accommodate a set of semiconductor dies arranged in a stack along a direction perpendicular to a plane of the slots, and the semiconductor dies may be offset from each other in a horizontal direction in the plane of slots so that one side of the stack defines a stepped terrace.

Abstract: In a hybrid integrated module, a semiconductor die is mechanically coupled face-to-face to an integrated device in which the substrate has been removed. For example, the integrated circuit may include an optical device fabricated on a silicon-on-insulator (SOI) wafer in which the backside silicon handler has been completely removed, thereby facilitating improved device performance and highly efficient thermal tuning of the operating wavelength of the optical device. Moreover, the semiconductor die may be a VLSI chip that provides power, and serves as a mechanical handler and/or an electrical driver. The thermal tuning efficiency of the substrateless optical device may be enhanced by over 100× relative to an optical device with an intact substrate, and by 5× relative to an optical device in which the substrate has only been removed in proximity to the optical device.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

Abstract: A multi-chip module (MCM) includes a stack of chips that are coupled using optical interconnects. On a first surface of a middle chip in the stack, there are: a first optical coupler, an optical waveguide, which is coupled to the first optical coupler, and a second optical coupler, which is coupled to the optical waveguide. The first optical coupler redirects an optical signal from the optical waveguide to a first direction (which is not in the plane of the first surface), or from the first direction to the optical waveguide. The second optical coupler redirects the optical signal from the optical waveguide to a second direction (which is not in the plane of the first surface), or from the second direction to the optical waveguide. An optical path associated with the second direction passes through an opening in a substrate in the middle chip.

Abstract: An optical device that includes multiple optical modulators having target operating wavelengths that are distributed over a band of wavelengths and actual operating wavelengths is described. For example, the target operating wavelengths of adjacent optical modulators may be separated by a wavelength increment. Moreover, because of differences between the actual operating wavelengths and the target operating wavelengths of the optical modulators, tuning elements may be used to tune the optical modulators so that the actual operating wavelengths match corresponding carrier wavelengths in a set of optical signals. Furthermore, control logic in the optical device may assign the optical modulators to the corresponding carrier wavelengths based at least on differences between the carrier wavelengths and the actual operating wavelengths, thereby reducing an average tuning energy associated with the tuning elements.

Abstract: An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips.

Abstract: A system includes optical modules. Each module includes a different base and one or more module waveguides on the base. Module waveguides from different modules are aligned such that the aligned module waveguides exchange light signals. At least a portion of one of the aligned module waveguides is between the base of one of the modules and the base of another module. First electronics operate a transmitter on a first one of the optical modules so as to generate one of the light signals. Second electronics operate a receiver on a second one of the modules such that the electronics generate an electrical signal in response to the receiver receiving one of the light signals.

Abstract: A multi-chip module (MCM) is described in which at least two substrates are mechanically coupled by an adhesive layer that maintains alignment and a zero (or near zero) spacing between proximity connectors on surfaces of the substrates, thereby facilitating high signal quality during proximity communication between the substrates. In order to provide sufficient shear strength, the adhesive layer has a thickness that is larger than the spacing. This may be accomplished using one or more positive and/or negative features on the substrates. For example, the adhesive may be bonded to: one of the surfaces and an inner surface of a channel that is recessed below the other surface; inner surfaces of channels that are recessed below both of the surfaces; or both of the surfaces. In this last case, the zero (or near zero) spacing may be achieved by disposing proximity connectors on a mesa that protrudes above at least one of the substrate surfaces.