Abstract: There are provided systems and methods for using fuel-rich partial oxidation to produce an end product from waste gases, such as flare gas. In an embodiment, the system and method use air-breathing piston engines and turbine engines for the fuel-rich partial oxidation of the flare gas to form synthesis gas, and reactors to convert the synthesis gas into the end product. In an embodiment the end product is methanol.

Abstract: A method of increasing image dynamic range by breaking each pixel into two or more time displaced samples that are presented to the display in synchronization with appropriate illumination.

Abstract: A system and method for managing memory in display processing circuit for use with a color sequential display. The system comprises: a shared memory; and a storage queue coupled to the shared memory, wherein the storage queue includes: a system for receiving and storing alternating packets of color-specific video data in the storage queue; and a system for separately reading contiguous sets color-specific packets from the storage queue to the shared memory.

Abstract: A uniform phase relation restoration method for a. scrolling color projection system wherein the addressing sequence of an LCD panel is altered to change the sweep rate of any one primary color relative to the other two primary colors to momentarily increase the sweep speed of the one color channel while correspondingly decreasing the sweep speed of the other two color channels.

Abstract: An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.

Abstract: A method of increasing image dynamic range by breaking each pixel into two or more time displaced samples that are presented to the display in synchronization with appropriate illumination.

Abstract: A prism is mounted onto a motor without regard to its rotation angle relative to the motor index. Its position is electronically set later after construction of the optical path. A motor controller is used to control the rotation of the prism. This motor controller keeps the prism spinning at a constant velocity and positions the prism phase (rotation angle versus time). A variable offset is used to position the absolute prism rotation as a function of time. The phase may be advanced or delayed by an operator during set up. Each prism has its own phase. The phase of each prism in the system is set so that the illumination pattern correctly matches the video addressing of the panel. This is a one time set up during construction. The correct positions are set, and stored in non-volatile memory for life.

Abstract: A uniform phase relation restoration method for a. scrolling color projection system wherein the addressing sequence of an LCD panel is altered to change the sweep rate of any one primary color relative to the other two primary colors to momentarily increase the sweep speed of the one color channel while correspondingly decreasing the sweep speed of the other two color channels.

Abstract: An address generator for a pixel shuffler used in a relective liquid crystal display (RLCD) digital video system, and a pixel shuffler incorporating such an address generator. The address generator includes a small, dual port SRAM 160×8, a combinatorial converter having a pair of inputs and an output representing a predetermined relationship of the inputs, a pixel counter with a pair of decoders, a line counter, a computing block for selectively implementing a mirror reflection of the pixel addresses, as well as a plurality of D flip flops and logic elements. The pixel shuffler operates in read-modify-write mode, whereby any address location of memory is read and immediately overwritten with the new data. This permits operation with only one bank of SRAM 320×96 rather than the customary two banks for prior art pixel shufflers using the so-called Ping Pong method.

Abstract: A system and method for controlling video data being communicated between a shared memory device and a plurality of process queues via a bi-directional bus. The system comprises a row address generator for associating a row address with each process queue; a system for determining a fullness of each process queue; a scheduling system for selecting a process queue to communicate with the shared memory device based on the determined fullness of each process queue; and a controller for causing the shared memory device to communicate with the selected process queue and for causing video data to be burst between the shared memory device and the selected process queue.

Abstract: A system and method for managing memory in display processing circuit for use with a color sequential display. The system comprises: a shared memory; and a storage queue coupled to the shared memory, wherein the storage queue includes: a system for receiving and storing alternating packets of color-specific video data in the storage queue; and a system for separately reading contiguous sets color-specific packets from the storage queue to the shared memory.

Abstract: A prism is mounted onto a motor without regard to its rotation angle relative to the motor index. Its position is electronically set later after construction of the optical path. A motor controller is used to control the rotation of the prism. This motor controller keeps the prism spinning at a constant velocity and positions the prism phase (rotation angle versus time). A variable offset is used to position the absolute prism rotation as a function of time. The phase may be advanced or delayed by an operator during set up. Each prism has its own phase. The phase of each prism in the system is set so that the illumination pattern correctly matches the video addressing of the panel. This is a one time set up during construction. The correct positions are set, and stored in non-volatile memory for life.

Abstract: In an electro-optic display device, such as a liquid crystal display device which serves as a modulator for projected light, a global DAC controlled ramp generator is used in conjunction with track and hold circuit for each column of the display to convert incoming digital display signals to analog signals for all columns. Row address circuitry addresses each row of the display, thereby to address the individual pixels of the display device with such analog signals. The limitation on an increase in frame rate, resulting from the finite conversion time (cycle time) of the DAC, is overcome by reducing the grey scale resolution, thus reducing the number of times that the DAC must convert a digital number to an analog voltage during each ramp cycle, and restoring the original resolution using temporal “dithering”—i.e., interpolation between the brightness levels of pixels in successive frames.

Abstract: In an electro-optic display device, such as a liquid crystal display device which serves as a modulator for projected light, a global ramp generator is used in conjunction with track and hold circuits to convert incoming digital display signals to analog signals, and to address the individual pixels of the display device with such analog signals. A plurality of column drivers, each coupled to the ramp generator and to the pixels in a column of the display device, track and hold the ramp voltage signal when it reaches a value corresponding to the desired brightness level of a particular pixel in the respective column. At least one current source is provided, coupled to the signal source output, for supplying current to the signal source output, as needed, to compensate for switching the capacitive load of the column drivers on and off. As a result, transient voltages in the ramp signal are avoided.

Abstract: A circuit that is easily configured to convert from a progressive scan image, e.g., at a resolution of 1280.times.720, to an interlaced image scan, e.g., at an interlaced resolution of 1920.times.1080 (1920.times.540 per field), or visa-versa. One arrangement of the circuit employs multiplexers so that the two conversion modes share the available hardware. The circuit is only marginally more complex than a circuit that can only do the conversion in one direction. The quality of the progressive-to-interlace conversion is acceptable for high-end interlaced display systems and the quality of the interlace-to-progressive conversion is at least high enough for "mid-range" progressive display systems.