Abstract: Systems, methods and apparatuses for embodiments of a transformation engine for structured documents are disclosed. More specifically, instruction code may be generated by a compiler from transformation instructions for a structured document. Embodiments of the transformation engine may comprise hardware circuitry operable to execute the instruction code to process a structured document according to the transformation instructions such that output for an output document is generated.

Abstract: Systems, methods and apparatuses for embodiments of a transformation engine for structured documents are disclosed. More specifically, instruction code may be generated by a compiler from transformation instructions for a structured document. Embodiments of the transformation engine may comprise hardware circuitry operable to execute the instruction code to process a structured document according to the transformation instructions such that output for an output document is generated.

Abstract: A system includes a virtual caching mechanism. A virtual cache is mapped to an address range separate from the main memory address range within a cacheable address space of the system. Regenerable data may be generated from source data and may be allocated space in the virtual cache. The CPU may fetch the data from the virtual cache (and the data may be supplied by a control circuit monitoring the CPU interface for addresses within the address range corresponding to the virtual cache). The data may be cached in a CPU cache, but may not be stored in the main memory. Thus, the CPU may have access to the regenerable data via the CPU cache, but main memory locations may not be required to store the regenerable data. If the regenerable data is replaced in the CPU cache and subsequently requested by the CPU, the regenerable data may be regenerated and supplied to the CPU.

Abstract: In a computer system, a multi-port bus controller interposed between a CPU, system memory, and an expansion bus detects when a CPU access is to non-cacheable address space and begins a bus cycle to access the data before receiving a "miss" from a cache coupled to the CPU. By detecting non-cacheable address space independently and in parallel with the cache miss determination, the multi-port bus controller saves from one to three clock cycles in each bus cycle that accesses non-cacheable address space.

Abstract: A spin buffer and associated method assure data integrity in shared resources in a computer system. Concurrent accesses to different semaphores by different devices are allowed. Lock and identification data within the semaphore is cached in the spin buffer so a device requesting access to a shared resource that corresponds to a semaphore that is represented in the spin buffer may determine whether any other device has ownership of the shared resource by accessing the data within the spin buffer, rather than reading from the semaphore. By caching semaphore lock information and allowing concurrent accesses to different semaphores by different devices, enhances system performance is achieved.

Abstract: A cache bus snoop protocol optimizes performance of a multiprocessor computer system with multiple level two caches by allocating windows of cache bus snoop activity on a need basis. When a cycle to cacheable address space is requested, the cache bus is granted only after the necessary snoop and write-back cycles are completed. During the snoop and write-back cycles, snoop activity by other devices in inhibited.