Abstract: Described herein are an electronic device and method for constructing same in which a rolled stacked electronic package includes one or more surface mounted embedded die modules. When the package is folded, the embedded die module and another surface mounted module are in contact with one another. The package increases circuit density and reduces microelectronic circuit size.

Abstract: Interconnect circuitry is formed on a selected face of several separate layered electronic assemblies simultaneously. This circuitry interconnects the I/O leads on each assembly, and it is formed by the steps of: (a) placing a plurality of the assemblies in a fixture with spacers between each assembly; (b) aligning to a single plane, one face of each assembly in the fixture on which the circuitry is to be formed; (c) mechanically squeezing the assemblies and spacers together with the fixture such that the aligned faces are held in the single plane and are exposed; (d) depositing and patterning layers of insulative and conductive materials on all of the exposed faces in the fixture; and (e) severing the layers between the faces in the space provided by the spacers. With this process, beading effects in materials that are spun onto the assemblies are eliminated; handling damage to the assemblies is eliminated; and the time and expense of processing one assembly separately is cut by several hundred percent.

Abstract: Layered electronic assemblies are fabricated from a plurality of integrated circuit chips that have respective thicknesses which vary from chip to chip, and have I/O leads which are offset from one edge of the chip on which they lie by respective distancess which vary from chip to chip.

Abstract: A layered electronic assembly contains a plurality of integrated circuit chips that are arranged in a stack; respective adhesive layers interleave the chips and hold them together; and I/O leads on the chips extend to one face of the stack. Also, the chips in the stack have respective thicknesses which vary from chip to chip; the I/O leads are offset from one edge of the chip on which they lie by respective distances which vary from chip to chip; the adhesive layers in the stack have respective thicknesses which compensate for the thickness variations in the chips such that the I/O leads on adjacent chips are spaced by predetermined distances along the stack face; and the chips are shifted relative to one another such that their one edge is misaligned while their I/O leads are aligned on the stack face. This layered electronic assembly uses 100% of the electrically functional chips which are cut from a semiconductor wafer without sacrificing any accuracy with which the I/O leads are aligned on the stack face.