Abstract: A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency.

Abstract: A voltage translation circuit translates an input signal having a first voltage level and a second voltage level to an output signal having the second voltage level and a third voltage level respectively. The voltage translation circuit according to the present invention includes a regenerative circuit having a first terminal and a second terminal. The voltage level at the first terminal increases responsive to the voltage level at the second terminal decreasing. The voltage level at the second terminal increases responsive to the voltage level at the first terminal decreasing. The voltage level at the first terminal defines the output signal. A first switch is coupled to the first terminal of said regenerative circuit, such that closing the first switch decreases the voltage level at the first terminal. A second switch is coupled to the second terminal of said regenerative circuit, such that closing the second switch decreases the voltage level at the second terminal.

Abstract: Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action.

Abstract: A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.

Abstract: A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.

Abstract: A sensing amplifier that works over a large operating frequency having a plurality of reference inputs, at least one signal input and at least one signal output, where the amplifier comprises a plurality of transistors to internally compare the signal input to the average value of the reference inputs and producing an output based on the comparison. In some cases, the output can be a latched binary signal.

Abstract: A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

Abstract: A circuit for delivering an accurate reference current independent of operating frequency that is implementable on-chip and that is relatively insensitive to process and temperature variations. A frequency source controls a rate of charge transfer via a switched capacitor to generate a constant current over different frequencies. A complimentary doped FET provides a band gap voltage imposed over a known resistance to generate the output current.

Abstract: A method of self calibration for a segmented digital-to-analog converter is provided. The segmented digital-to-analog converter converts a digital input code to an analog output consisting of an analog output step and an analog calibration factor. The method comprises the step of determining a trim value for each segment of a segmented DAC. The method continues by storing the trim values in memory. Then, the trim values for a plurality of segments preselected to be enabled by a given digital input signal are summed, thereby producing a digital calibration factor associated with each given digital input signal. Last, storing each digital calibration factor in memory at an address corresponding to the associated digital input signal.

Abstract: A constant-current generator circuit includes an output circuit and a control circuit, with the control circuit producing a control voltage to define a reference current through the output circuit. An important feature is that the control circuit uses a pair of transistors having different threshold voltages in generating the control voltage. The circuit is formed using CMOS technology, and the difference in threshold voltage may be produced by doping the polysilicon gate of an N-channel or P-channel field effect transistor. The step of doping to produce the change in threshold voltage is compatible with the standard processing for the CMOS device. In a preferred embodiment, the control circuit uses two pairs of control transistors, each pair having differing thresholds. One pair is P-channel and the other N-channel. These pairs are in parallel, the P-channel pair connected to the positive supply and the N-channel pair to the negative supply or ground.

Abstract: According to the preferred embodiment, a self-biased phase-locked loop is provided that overcomes the limitations of the prior art bias methods and apparatus. In general, a self-biased current controlled semiconductor device, typically a current controlled oscillator, is self biased by the use of a first feedback path, typically provided by a phase-locked loop, where the feedback path provides a control current for controlling the current controlled device. A second feedback path, typically a pair current mirrors, serves as a bias loop having unity gain. The bias loop provides a bias current that is responsive to the control current. This device has the advantage of being self biasing, thus no other biasing circuitry is required.

Abstract: An integrated current reference circuit provides a current output with a predetermined temperature coefficient, suitably zero, to provide constant current over temperature variations. The circuit is formed of only Field Effect Transistors (FETs), allowing the circuit to be implemented using conventional CMOS fabrication techniques. A current mirror provides a reference current in both branches of the circuit. The output of the current mirror is coupled to a circuit providing an imbalance in resistance between the two branches, and an offsetting imbalance in voltages between the two branches, resulting in a reference current that has a predetermined temperature coefficient. An output current is provided which is proportional to the reference current and thus has the same temperature coefficient as the reference current.

Abstract: An electrostatic discharge suppression circuit is presented for an integrated circuit chip intended for subsequent functioning within a multi-level power supply environment. The suppression circuit includes a clamping circuit, discharge means and a trigger circuit. The clamping circuit shunts an electrostatic discharge at an input and/or output node of the integrated circuit chip to a common node of the suppression circuit. The discharge means is coupled to the common node for dissipating the electrostatic discharge shunted thereto. The trigger circuit is connected to both the common node and the discharge means and includes regenerative feedback for fast turn on of the discharge means as the electrostatic discharge is shunted to the common node such that damage to the integrated circuit chip due to the electrostatic discharge is prevented. An inhibit circuit is coupled to the discharge means for selective inhibiting of the discharge means in response to an inhibit protection signal.

Abstract: Calibration systems and techniques for analog phase-lock loops (PLLs) providing the capability to dynamically maintain a constant damping factor. Damping factor is calibrated by automatically setting a reference bias current I.sub.r to the PLL's charge pump such that the charge current I.sub.c output therefrom maintains the desired PLL damping characteristic. The technique presented involves selecting a known first frequency F.sub.1 and allowing the PLL circuit to reach steady state, after which a known second frequency F.sub.2 is applied and the PLL circuit is monitored to determine whether steady state at this second frequency F.sub.2 is accomplished within a predetermined target time T.sub.x, which corresponds to the desired damping factor. The determination of whether lock occurs within the target time T.sub.x is then employed to automatically set the reference current I.sub.r.

Abstract: An electrical current-switching driver circuit is provided for switching current through an inductive memory write head on a memory storage device. The driver circuit provides means for reducing distortion in the output current waveform and for minimizing occurrences of breakdown in the switching transistors in the circuit. The circuit uses AC coupling circuitry and small DC holding currents to linearize the current transition during switching transients, thereby eliminating discontinuities which would otherwise appear in the head current output waveform, midway through the switching transients.

Abstract: A phase-controlled loop system having a charge pump circuit including a current mismatch measurement circuit and a current compensation circuit for equalizing the amplitude of positive current pulses and the amplitude of negative current pulses output when the phase-controlled loop system is in phase-locked condition. The current mismatch measurement circuit includes duplicate complementary current sources with characteristics and biasing substantially identical to that of the primary current sources providing the positive current and the negative current to the output node of the charge pump circuit. At the common connected node between the duplicate complementary current sources an error current is produced having an amplitude equal to the difference between the amplitude of the positive current pulses and the amplitude of the negative current pulses to the output node.

Abstract: A filter network is presented for a phase-locked loop (PLL) circuit having a voltage controlled oscillator (VCO) with a control input and a bias input. The filter network includes a conventional filter circuit that provides a "pole" and a "zero" to the transfer function of the PLL circuit. The conventional filter circuit is coupled between the control input of the VCO and ground. An additional filter circuit is also coupled to the control input of the VCO, and to a bias input of the VCO. This additional filter circuit provides at least one additional "zero" to the PLL transfer function to extend the frequency range of the PLL circuit without impairing circuit stability. A transconductance amplifier is preferably employed within the additional filter circuit to facilitate tailoring of the open loop gain of the filter/oscillator circuitry.

Abstract: A ring oscillator circuit which provides an output signal having a substantially constant, fifty (50%) percent duty cycle. The circuit includes a plurality of cascaded inverting stages, each of which has an input circuit for detecting an output voltage of a preceding inverting stage. One inverting stage provides a voltage to an output node. A clamping circuit, coupled to the output node, provides current to the output node whenever the instantaneous voltage output at the output node departs from a threshold voltage of a subsequent logic circuit. The current is such as to clamp the average voltage output to the threshold voltage. The plurality of cascaded inverting stages is coupled to power supply voltage across capacitor configured transistors. The ring oscillator circuit can be employed within a voltage controlled oscillator.

Abstract: An analog receiver circuit suitable for use with a flash analog-to-digital converter is described. A first stage of the receiver acts essentially as a voltage follower, receiving the centertap voltage of a flash A/D converter resistor ladder, and maintaining an internal reference voltage substantially equal to the centertap voltage over time. A second stage of the analog receiver acts as centering means, receiving an analog signal and centering it with respect to the internal reference voltage provided by the first stage. The receiver is thus able to provide an analog signal to the flash A/D converter which is dynamically centered with respect to the converter's operating voltage, thereby reducing DC offset. Moreover, introducing the analog signal at the second stage minimizes the bandwidth-limiting elements between this input signal and the DC-centered output signal. Thus DC offset is further reduced and operating frequencies of 500 MTz or greater are possible.

Abstract: A system and method is provided for estimating the bit error rate of a data signal which has been reconstructed from a received data signal. The system comprises (i) logic for determining timing degradation and amplitude degradation of the received data signal; (ii) an actual bit error rate calculator for calculating the actual bit error rate of the reconstructed data signal; (iii) an instantaneous bit error rate calculator for estimating a bit error rate of the reconstructed signal using the timing degradation and the amplitude degradation; (iv) a first integrator for integrating the estimated bit error rate; (v) a comparator for comparing the integrated estimated bit error rate with the actual bit error rate and outputting an error signal which modifies the estimated bit error rate; and (vi) a second integrator for integrating the estimated bit error rate. The time constant associated with the second integrator is shorter than the time constant associated with the first integrator.