Abstract: Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

Abstract: Tungsten studs of a size comparable to vias are provided to integrate and interface between copper and aluminum metallization layers in an integrated circuit and/or package therefor by lining a via opening, preferably with layers of tantalum nitride and PVD tungsten as a barrier against the corrosive effects of tungsten fluoride on copper. The reduced size of the tungsten studs relative to known interface structures allows wiring and connection pads to be formed in a single aluminum layer, improving performance and reducing process time and cost.

Abstract: A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Abstract: A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

Abstract: A process is disclosed for producing a metal-organic polymer combination by contacting the polymer with a plasma followed by an aqueous solution of a metal salt. In one embodiment a water or nitrous oxide plasma is used to treat a polyimide or a fluorinated polymer. The polymer is combined with a metal cation, the metal being a catalyst for a conventional electroless coating after which it is contacted with an electroless metal plating bath for the formation of electrical circuits and especially for plating high aspect ratio vias in microcircuits. Unlike the conventional electroless process, the cationic catalytic metal is not reduced to a zero valent metal catalyst prior to the application of the electroless metal coating solution.The process also improves the wettability of the polymer, especially the fluorinated polymer and is especially useful in improving the wettability of high aspect ratio vias.

Abstract: A process chamber having voltage driven electrodes, e.g. plasma chamber, can be made self cleaning of particle contamination by appropriate design of the workpiece or electrode surface to provide protuberances, grooves or tapers thereon which result in a predetermined pattern in the electrostatic potential within the process chamber which can trap particulate contamination in preselected regions within the plasma chamber. These particles can then be channeled out of the process chamber through a pump port.

Abstract: Method for water vapor plasma treating the surface of a polymer body to enhance the adhesion of a first and second polymer surface. The method is particularly useful for polyimide surfaces.