Patents by Inventor John E. Kelly
John E. Kelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12239675Abstract: Provided herein, inter alia, are compositions of short chain fatty acid (SCFA)-producing microorganisms and methods of making and using the same to inhibit pathogenic bacterial populations in the gastrointestinal tracts of an animal and additionally promote improvement of one or more metrics in an animal, such as increased bodyweight gain, decreased feed conversion ratio (FCR), improved gut barrier integrity, reduced mortality, reduced pathogen infection, and reduced pathogen shedding in feces.Type: GrantFiled: October 16, 2020Date of Patent: March 4, 2025Assignee: INTERNATIONAL N&H DENMARK APSInventors: John Thomas Gannon, Michael W. Bostick, Amanda Chan, Raymond E. Jackson, Victoria Vallejo Kelly, Alexander D. Kopatsis, Claus Lang, Qiong Wang, Julia Yager, Rick W. Ye
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Patent number: 12226250Abstract: Systems and methods for determining body composition by combining dual-energy x-ray (DXA) technology with three-dimensional (3D) optical technology and/or bioimpedance technology. A multi-modality scanning system may include a dual-energy x-ray source and an x-ray detector mounted to opposing sides a c-arm and configured to scan a patient on a optically translucent table. The system may also include one or more 3D optical imaging devices to capture 3D optical images of the patient substantially concurrently with the emission of the dual energy x-rays. A bioimpedance machine may also be included in the multi-modality scanning system. Data based on the dual-energy x-rays may be combined with the data from the 3D optical images and/or the bioimpedance data to generate values of at least three compartments selected from: bone, fat tissue, lean tissue, dehydrated lean tissue, and water.Type: GrantFiled: March 22, 2018Date of Patent: February 18, 2025Assignees: Hologic, Inc., The Regents of the University of CaliforniaInventors: Kevin E. Wilson, John A. Shepherd, Bennett K. Ng, Mark Guetersloh, Chao Huang, Thomas L. Kelly, Wei Wang, Howard Weiss
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Patent number: 9245813Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.Type: GrantFiled: January 30, 2013Date of Patent: January 26, 2016Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K Sinha, Kevin A. Splittstoesser, Timothy A. Tofil
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Patent number: 9111899Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip.Type: GrantFiled: September 13, 2012Date of Patent: August 18, 2015Assignee: LenovoInventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K. Sinha, Kevin A. Splittstoesser, Timothy J. Tofil
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Publication number: 20140210068Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K. Sinha, Kevin A. Splittstoesser, Timothy A. Tofil
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Publication number: 20140070393Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors.Type: ApplicationFiled: September 13, 2012Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K. Sinha, Kevin A. Splittstoesser, Timothy J. Tofil
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Patent number: 8367478Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.Type: GrantFiled: June 2, 2011Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, David R. Motschman
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Publication number: 20120306088Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.Type: ApplicationFiled: June 2, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gerald K. BARTLEY, Charles L. JOHNSON, John E. KELLY, III, David R. MOTSCHMAN
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Patent number: 4710031Abstract: A microtiter plate reader is disclosed which allows visual examination of the contents of the wells of a microtiter plate having an array of wells. The microtiter plate reader includes supporting means for supporting the microtiter plate with the wells opening generally upwardly and a light emitting surface is adapted to extend under a microtiter plate so held. Regions of reduced light emission on the light emitting surface are arranged in an array corresponding in relative position to a selected portion of the array of microtiter plate wells. Locator means are provided for locating the microtiter plate with respect to the array of regions of reduced light emission to allow selective alignment of the wells with the dark regions, providing a dark background to the bottom of the wells which are then illuminated indirectly. The wells can be illuminated directly when the dark regions are out of alignment with the wells.Type: GrantFiled: July 31, 1985Date of Patent: December 1, 1987Assignee: Lancraft, Inc.Inventors: John E. Kelly, Don C. Jones, Frederick R. Tuck, William A. Zimmermann, Kenneth R. Clark