Patents by Inventor John E. Kelly

John E. Kelly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performance
    Patent number: 9245813
    Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K Sinha, Kevin A. Splittstoesser, Timothy A. Tofil
  • Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacks
    Patent number: 9111899
    Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 18, 2015
    Assignee: Lenovo
    Inventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K. Sinha, Kevin A. Splittstoesser, Timothy J. Tofil
  • HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN ETCHED SILICON WAFER TROUGHS FOR ENHANCED THERMAL PERFORMANCE
    Publication number: 20140210068
    Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.
    Type: Application
    Filed: January 30, 2013
    Publication date: July 31, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K. Sinha, Kevin A. Splittstoesser, Timothy A. Tofil
  • HORIZONTALLY AND VERTICALLY ALIGNED GRAPHITE NANOFIBERS THERMAL INTERFACE MATERIAL FOR USE IN CHIP STACKS
    Publication number: 20140070393
    Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, Joseph Kuczynski, David R. Motschman, Arvind K. Sinha, Kevin A. Splittstoesser, Timothy J. Tofil
  • Method and system for internal layer-layer thermal enhancement
    Patent number: 8367478
    Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: February 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, Charles L. Johnson, John E. Kelly, III, David R. Motschman
  • METHOD AND SYSTEM FOR INTERNAL LAYER-LAYER THERMAL ENHANCEMENT
    Publication number: 20120306088
    Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.
    Type: Application
    Filed: June 2, 2011
    Publication date: December 6, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerald K. BARTLEY, Charles L. JOHNSON, John E. KELLY, III, David R. MOTSCHMAN
  • Microtiter plate reader
    Patent number: 4710031
    Abstract: A microtiter plate reader is disclosed which allows visual examination of the contents of the wells of a microtiter plate having an array of wells. The microtiter plate reader includes supporting means for supporting the microtiter plate with the wells opening generally upwardly and a light emitting surface is adapted to extend under a microtiter plate so held. Regions of reduced light emission on the light emitting surface are arranged in an array corresponding in relative position to a selected portion of the array of microtiter plate wells. Locator means are provided for locating the microtiter plate with respect to the array of regions of reduced light emission to allow selective alignment of the wells with the dark regions, providing a dark background to the bottom of the wells which are then illuminated indirectly. The wells can be illuminated directly when the dark regions are out of alignment with the wells.
    Type: Grant
    Filed: July 31, 1985
    Date of Patent: December 1, 1987
    Assignee: Lancraft, Inc.
    Inventors: John E. Kelly, Don C. Jones, Frederick R. Tuck, William A. Zimmermann, Kenneth R. Clark