Abstract: A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer is covered by a sidewall spacer which protects a portion of the substrate from attack by the etchant used to form the trench. The trench is filled with a trench fill material by selective deposition using a seeding material formed on the sidewall of the trench as a nucleation site. After the trench is filled, the sidewall spacer is removed and the underlying substrate is oxidized to form an electrical insulation region around the upper portion of the trench. The mask layer is removed and the remaining substrate is doped using the insulation region surrounding the trench as a dopant mask.

Abstract: A transversly injected quasi-floating gate memory cell. A memory transistor in bulk silicon has a channel region in bulk silicon which is capacitatively coupled both to a thin polysilicon quasi-floating gate and to an overlying word line. The thin polysilicon level which comprises the floating gate is not coterminous with the channel region of the memory transistor, but the quasi-floating gate portion of the thin polysilicon layer is connected, through a polysilicon channel region, to a write bit line. The overlying word line thus addresses both the write transistor in a thin polysilicon level and also the memory transistor itself in the substrate.