Abstract: Conventional routing switchers have employed a fixed architecture, i.e. the input and output connectors of the switching matrix are fixed in function. Prior art routing switchers use fixed matrix sizes. This invention uses a variable input/output architecture to enable multiple matrix sizes to be implemented in a single product. Switches are used to connect a subset of input and output connectors to either an input pin or an output pin. These switches allow users to select the number of input connectors and output connectors available for their particular application. The invention enables a single product to replace a range of routing switchers of different sizes. The user can also reconfigure the routing switcher size should application requirements change. This allows the user to configure the routing switcher matrix size to exactly meet the application requirements.

Abstract: Conventional routing switchers have employed a fixed architecture, i.e. the input and output connectors of the switching matrix are fixed in function. Prior art routing switchers use fixed matrix sizes. This invention uses a variable input/output architecture to enable multiple matrix sizes to be implemented in a single product. Switches are used to connect a subset of input and output connectors to either an input pin or an output pin. These switches allow users to select the number of input connectors and output connectors available for their particular application. The invention enables a single product to replace a range of routing switchers of different sizes. The user can also reconfigure the routing switcher size should application requirements change. This allows the user to configure the routing switcher matrix size to exactly meet the application requirements.

Abstract: An architecture for switching reference generation uses a scanning sync separator to sample each output from the matrix outputs in turn to determine the format of each output. A controller selects an appropriate switch reference signal from among a plurality of switch reference signals according to the determined format and applies such selected switch reference signal to a crosspoint switch corresponding to the matrix output so that subsequent switches between matrix inputs are synchronous.

Abstract: An input expansion for a crosspoint switch module incorporates a plurality of crosspoint switch ICs within the switch module so that the crosspoint switch module may receive a plurality of input differential signals. The crosspoint switch module includes a module driver circuit which, when enabled by a module enable signal, couples a differential current signal to an output. Each crosspoint switch includes an emitter follower configured transistor circuit for receiving one of the input differential signals and providing an output differential signal and a switch transistor circuit configured as a saturated switch for receiving the output differential signal and providing the differential current signal when enabled by a switch enable signal. Only one of the crosspoint switches is enabled at a time so that only one of the crosspoint switches carries current.

Abstract: A circuit for preserving a predetermined timing relationship between a synchronization signal including periodic sync codes and a digital signal composed of successive frames of which the nominal duration is equal to the period of the sync codes includes a delay device connected to receive the digital signal. The delay device is selectively adjustable to impose a controllable delay on propagation of the digital signal. A FAW detector detects a frame alignment word in the digital signal, and a time measurement circuit measures the time that elapses between occurrence of a sync code and detection of a frame alignment word. A delay adjustment circuit is responsive to the time measurement circuit to adjust the delay imposed by the delay device.

Abstract: A circuit for driving a transmission line composed of first and second conductors, comprises input transistors for providing a differential signal, and first and second output transistors having their bases connected to receive the differential signal, their collectors connected to a first reference potential level, and their emitters connected to the first and second conductors respectively. An output enable circuit selectively places the output transistors either in a conductive condition, in which they apply the differential signal to the transmission line, or in a non-conductive condition, in which the isolate the transmission line from the input transistors.

Abstract: A crosstalk reduction circuit compensates for input to output capacitance coupling of each switch of a crosspoint matrix and for output to common level capacitance coupling for each integrated circuit chip that makes up the crosspoint matrix. Each input signal to the crosspoint matrix is capacitively scaled, summed and inverted to produce an "off" isolation compensation signal, and each output signal from the crosspoint matrix is capacitively scaled, summed and inverted to produce an output isolation compensation signal. Each compensation signal is resistively scaled for each output signal, and the scaled compensation signals are subtracted from the output signals to reduce the crosstalk in the output signals.

Abstract: A low power, differential ECL line driver has a switching network that applies a constant current source as the emitter load to only one of the output transistors at a time while applying a constant current source to the base of the other output transistor.