Abstract: Methods, systems, and devices for out-of-band authentication for multi-port memory systems are described. A multi-port memory system may grant host systems access to multiple ports of the memory system based on attestation with an authentication management controller that uses out of band (OOB) signaling to communicate with the memory system. For example, upon power up of the memory system, access to the memory system via the multiple ports may be limited, and some commands requested from host systems via the multiple ports may be denied. Increased access to the memory system via the multiple ports may be granted based on OOB signaling from the authentication management controller that attests each host system that is coupled with a respective port of the memory system. After a host system has been attested, the host system may be granted full access to a command set of the memory system.

Abstract: Methods, systems, and devices for security function management within a multi-port memory system are described. A memory system may include multiple ports each coupled with one or more host systems. The memory system may receive a namespace configuration indicating an allocation of one or more logical block addresses (LBAs) to one or more of the ports. The memory system may further receive one or more requests for access to one or more LBA ranges, and may perform an authorization procedure to authorize a single entity to provision and unlock corresponding LBA ranges. In some examples, LBA ranges may be locked by default on bootup of the memory system. In some cases, host systems may request a management controller to coordinate authorization, or may request authorization from a memory system directly using one or more credentials or identifiers. Further, a management port may be indicated via one or more commands.

Abstract: Methods, systems, and devices for port resource management within a multi-port memory system are described. A memory system may include multiple ports each coupled with one or more host systems. The memory system may receive a command defining a secure management port via an interface with a management controller or via another port. In some cases, the defined management port may be a dedicated port, or may be selected during one or more power-on procedures. The command may also indicate a quantity of ports to be activated, and may be based on an attestation of one or more host systems. In some examples, the memory system may use the management port to receive additional communications and commands. For example, the management port may receive and execute commands for resource allocation, additional configurations, sub-system operations including power management and reset, or for diagnostic functions, among other operations.

Abstract: Methods, systems, and devices for security management modes of a multi-port memory system are described. A multi-port memory system may be configured to operate according to one or more security modes that adjust access by host systems to the multiple ports of the memory system. For example, in a first mode, which may be referred to herein as a port security management mode, the memory system may restrict access by unauthenticated host systems to ports of the memory system, such that any unauthenticated host systems have no access to the memory system via the ports or are limited to a relatively primitive set of commands until the host systems are authenticated. In a second mode, which may be referred to herein as an operational mode, any host systems coupled with ports of the memory system are granted, without authentication, full access to a command set supported by the memory system.

Abstract: Methods, systems, and devices for power loss notification (PLN) power processing for memory systems are described. A memory device may be coupled with power loss backup circuitry that is external to the memory device. The power loss backup circuitry may detect a loss of a power supply and may utilize a PLN to notify the memory device of the power loss. The power loss backup circuitry may provide a backup power supply to the memory device while the memory device prepares for shutdown. The memory device may use the PLN, a power loss acknowledgment (PLA) indication, and a logging mechanism to verify that a duration over which the backup power is supplied is sufficient to support a complete shutdown operation, including the reliable flush of data to non-volatile memory without error. The PLN and logging mechanism described herein provides for reliable and efficient power loss processing.

Abstract: Methods, systems, and devices for dynamic allocation of a host memory buffer are described. A host system may allocate a portion of memory of the host system to a buffer for use by a memory system. In some cases, the allocation of the memory of the host system may be based on a setting indicated by the memory system, which may indicate one or more parameters associated with the buffer. The memory system may use the buffer for one or more operations, such as read, write, or system operations. In some examples, the host system may indicate one or more resources available at the host system for allocating to the buffer. The memory system may communicate a second setting including updated parameters associated with the buffer based on the indication of available resources, and the host system may allocate one or more additional resources in response to the updated parameters.

Abstract: Methods, systems, and devices for single level cell write buffer extension control are described. A host device may indicate a delay to be observed between write operations to a memory system. The memory system may perform random read operations or read operations for garbage collection during these delays, which allow the memory system to allocate space for a write buffer, such as a single-level cell (SLC) write buffer, even when performing a large quantity of write commands as part of a sequential write command. Additionally, by allocating space for the write buffer, the memory system may be able to keep writing to memory cells in accordance with the first write operation type, such as an SLC type, for longer periods of time, which may improve the write speeds and decrease an overall latency associated with sequential write operations.

Abstract: Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.

Abstract: Methods, systems, and devices for thermal throttling of a memory system are described. The method may include the memory system operating according to a first performance state and determining, while the memory system operates according to the first performance state, whether a temperature metric of the memory system satisfies a first threshold corresponding to a second performance state. Further, the memory system may select, based on the temperature metric satisfying the first threshold, the second performance state from a set of three or more performance states and operate the memory system according to the second performance state based on selecting the second performance state.

Abstract: A processing device in a memory sub-system generates a set of media management data associated with a memory device of the memory sub-system. The processing device further causes the set of media management data to be stored in an ultra-high endurance storage class memory device of the memory sub-system.

Abstract: A processing device in a memory sub-system identifies a power loss event associated with the memory sub-system including a memory device and an ultra-high endurance storage class memory device. In response to the power loss event, the processing device further identifies a set of data corresponding to one or more in-flight operations associated with the memory device. The processing device further causes the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device. The processing device further causes execution of a data recovery operation using the set of data corresponding to the one or more in-flight operations to be stored in the ultra-high endurance storage class memory device.

Abstract: A processing device in a memory sub-system receives host data to be stored in a memory sub-system including a memory device and an ultra-high endurance storage class memory device. The processing device further causes the host data to be stored in a host data buffer of the ultra-high endurance storage class memory device. The processing device causes a first portion of the host data stored in the host data buffer to be overwritten during a buffer tenure. In response to determining that a second portion of the host data satisfied a buffer tenure requirement, causing the second portion of the host data to be written from the host data buffer to the primary memory of the memory device.

Abstract: A processing device in a memory sub-system determine that an amount of host data in a portion of an ultra-high endurance storage class memory device configured as a program buffer satisfies a buffer threshold criterion. The processing device further initiates an initial program pass of first host data from the program buffer to a portion of a memory device configured as primary memory and initiates a final program pass of the first host data from the program buffer to the primary memory.

Abstract: A memory sub-system that supports both PCIe and ethernet, without a separate switch or bridge, includes a processing device to detect a first host system connected to a first interface port of the plurality of interface ports of the memory device. The processing device further detects a second host system connected to a second interface port of the plurality of interface ports. The processing device further assigns a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigns a second subset of the plurality of VFs to the second host system using SR-IOV. The processing device further allocates a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocates a second corresponding range of LBAs to each VF of the second subset of VFs.

Abstract: Methods, apparatuses and systems related to dynamically controlling flow and implementation of operations for each function. The apparatus may use a timing parameter to initiate implementation of queued commands. The apparatus may include a queue arbiter configured to dynamically adjust the timing for each function according to a feedback that corresponds to resources consumed in implementing preceding commands for the corresponding function.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.