Abstract: Methods, apparatuses and systems related to dynamically controlling flow and implementation of operations for each function. The apparatus may use a timing parameter to initiate implementation of queued commands. The apparatus may include a queue arbiter configured to dynamically adjust the timing for each function according to a feedback that corresponds to resources consumed in implementing preceding commands for the corresponding function.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of a plurality of interface ports of a memory device, detecting a second host system connected to a second interface port of the plurality of interface ports, allocating a first range of logical block addresses (LBA) to one or more virtual functions (VFs) assigned to the first host system, and allocating a second range of LBAs to one or more VFs assigned to the second host system, wherein the first host system is to access the first range of LBA of the memory device concurrently with the second host system accessing the second range of LBA of the memory device, and wherein the first range of LBAs is different than the second range of LBAs.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of the plurality of interface ports of the memory device, the first host system is one of a plurality of host systems. Detecting a second host system connected to a second interface port of the plurality of interface ports, the second host system is one of the plurality of host systems. Assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigning a second subset of the plurality of VFs to the second host system using SR-IOV. Allocating a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocating a second corresponding range of LBAs to each VF of the second subset of VFs.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.

Abstract: An electrical board includes a ground layer, a power layer, a first signal layer, a top surface, first and second vias that extend substantially perpendicularly to the top surface through the ground layer, the power layer and the first signal layer, and one or more conductive traces disposed in the first signal layer, the one or more conductive traces lying between the first and second vias.

Abstract: A processing device to perform operations including detecting a first host system connected to a first interface port of the plurality of interface ports of the memory device, the first host system is one of a plurality of host systems. Detecting a second host system connected to a second interface port of the plurality of interface ports, the second host system is one of the plurality of host systems. Assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigning a second subset of the plurality of VFs to the second host system using SR-IOV. Allocating a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocating a second corresponding range of LBAs to each VF of the second subset of VFs.

Abstract: Systems and methods are disclosed for communicating data between a plurality of data storage devices. Multiple standalone data storage devices may be coupled to a data storage device docking station. A master data storage device may control the communication the communication of data between the standalone data storage devices. Slave data storage devices may communicated data based on one or more commands transmitted by the master data storage device.

Abstract: Systems and methods are disclosed for identifying disk drives and processing data access requests. A disk drive may be identified as an Advanced Host Controller Interface (AHCI) drive, a Non-Volatile Memory Express (NVME) drive, and/or an ATA packet interface (ATAPI) drive. Data access requests for the disk drive may be translated to NVME commands, AHCI commands, or ATAPI commands, based on whether the drive is identified as a NVME drive, an AHCI drive, and/or an ATAPI drive.

Abstract: An electrical board includes a ground layer, a power layer, a first signal layer, a top surface, first and second vias that extend substantially perpendicularly to the top surface through the ground layer, the power layer and the first signal layer, and one or more conductive traces disposed in the first signal layer, the one or more conductive traces lying between the first and second vias.

Abstract: Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based on priorities for the data access requests.

Abstract: Systems and methods are disclosed for configuring multi-line serial computer expansion bus communication links. A controller for a data storage device may receive one or more signals indicative of bifurcation settings from a configuration component or a host bus adapter may provide one or more signals indicative of bifurcation settings to the controller. The controller may receive configuration data from the BIOS based on the one or more signals and may configure the multi-line serial computer expansion bus communication links based on the configuration data.

Abstract: The present invention relates to providing reliable power to a storage device. In one embodiment, the storage device employs dual external power supplies. The power supplies may both provide power to the storage device. Alternatively, the power supplies may provide power in different configurations. One power supply may be a primary supply providing all or a majority of power, while the other power supply may be a backup. The storage device may comprise high efficiency DC-to-DC converters to permit the use of lower power-rated external power supplies. A staggered startup procedure by the storage device may be implemented to manage peak power draw. The storage device may be further configured to load balance and power share between the external power supplies. In addition, the storage device is configured to monitor the status of the external power supplies and send a notification if one or more of the power supplies fails.

Abstract: Systems and methods are disclosed for routing electrical signals in a printed circuit board (PCB), wherein the PCB includes a conductive ground layer, a conductive power layer and a conductive signal layer. A first volatile memory module and a memory receptacle are mounted to the top surface of the PCB, wherein the memory receptacle electrically connects a second volatile memory to vias connected to the memory receptacle that extend through the ground, power and signal layers. The controller board includes one or more conductive traces disposed in the signal layer between the first and second vias, wherein signals may flow through the vias to the first volatile memory.

Abstract: Systems and methods are disclosed for identifying disk drives and processing data access requests. A disk drive may be identified as an Advanced Host Controller Interface (AHCI) drive, a Non-Volatile Memory Express (NVME) drive, and/or an ATA packet interface (ATAPI) drive. Data access requests for the disk drive may be translated to NVME commands, AHCI commands, or ATAPI commands, based on whether the drive is identified as a NVME drive, an AHCI drive, and/or an ATAPI drive.

Abstract: Systems and methods are disclosed for processing data access requests received from a direct access storage (DAS) interface and/or a network access storage (NAS) interface. The data access requests may be received from the DAS interface and the NAS interface substantially simultaneously. The data access requests may be scheduled based on priorities for the data access requests.

Abstract: A data storage network is provided. The network includes a client connected to the data storage network; a plurality nodes on the data storage network, wherein each data node has two or more RAID controllers, wherein a first RAID controller of a first node is configured to receive a data storage request from the client and to generate RAID parity data on a data set received from the client, and to store all of the generated RAID parity data on a single node of the plurality of nodes.