Patents by Inventor John E. Sanchez

John E. Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Two-terminal reversibly switchable memory device
    Patent number: 11672189
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: June 6, 2023
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Two-terminal reversibly switchable memory device
    Patent number: 11063214
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 13, 2021
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20210193917
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: March 8, 2021
    Publication date: June 24, 2021
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20200259079
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Two-terminal reversibly switchable memory device
    Patent number: 10680171
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 9, 2020
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20190173006
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: January 30, 2019
    Publication date: June 6, 2019
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Two-terminal reversibly switchable memory device
    Patent number: 10224480
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20180130946
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 10, 2018
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Two-terminal reversibly switchable memory device
    Patent number: 9831425
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 28, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof
    Patent number: 9818939
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 14, 2017
    Assignee: ADESTO TECHNOLOGIES CORPORATION
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Yi Ma, Venkatesh P. Gopinath, Foroozan Sarah Koushan
  • Resistive Switching Devices Having a Switching Layer and an Intermediate Electrode Layer and Methods of Formation Thereof
    Publication number: 20160118585
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Yi Ma, Venkatesh P. Gopinath, Foroozan Sarah Koushan
  • Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof
    Patent number: 9252359
    Abstract: In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 2, 2016
    Assignee: Adesto Technologies Corporation
    Inventors: John R. Jameson, III, John E. Sanchez, Wei Ti Lee, Foroozan Sarah Koushan
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20150380642
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Two-terminal reversibly switchable memory device
    Patent number: 9159913
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE
    Publication number: 20150029780
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: August 19, 2014
    Publication date: January 29, 2015
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Two Terminal Re Writeable Non Volatile Ion Transport Memory Device
    Publication number: 20120087174
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, CHRISTOPHE J. CHEVALLIER, WAYNE KINNEY, ROY LAMBERTSON, STEVEN W. LONGCOR, JOHN E. SANCHEZ, JR., LAWRENCE SCHLOSS, PHILIP F.S. SWAB, EDMOND WARD
  • Method for fabricating multi-resistive state memory devices
    Patent number: 8062942
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 22, 2011
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John E. Sanchez, Jr., Philip Swab
  • Multi-resistive state memory device with conductive oxide electrodes
    Patent number: 7889539
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: February 15, 2011
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe Chevallier, John E. Sanchez, Jr., Philip Swab
  • Movable terminal in a two terminal memory array
    Patent number: 7701834
    Abstract: A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: April 20, 2010
    Inventors: Darrell Rinerson, Christophe Chevallier, John E. Sanchez, Jr., Lawerence Schloss
  • Multi-resistive state memory device with conductive oxide electrodes
    Patent number: 7633790
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 15, 2009
    Inventors: Darrel Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John E. Sanchez, Jr., Philip Swab