Patents by Inventor John E. Sanchez, Jr.

John E. Sanchez, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190173006
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: January 30, 2019
    Publication date: June 6, 2019
    Inventors: Darrell RINERSON, Christophe J. CHEVALLIER, Wayne KINNEY, Roy LAMBERTSON, John E. SANCHEZ, JR., Lawrence SCHLOSS, Philip SWAB, Edmond WARD
  • Patent number: 10224480
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Hefei Reliance Memory Limited
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20180130946
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 10, 2018
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 9831425
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: November 28, 2017
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20150380642
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 9159913
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: October 13, 2015
    Assignee: Unity Semiconductor Corporation
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, Jr., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20150029780
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: August 19, 2014
    Publication date: January 29, 2015
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Publication number: 20120087174
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: December 16, 2011
    Publication date: April 12, 2012
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: DARRELL RINERSON, CHRISTOPHE J. CHEVALLIER, WAYNE KINNEY, ROY LAMBERTSON, STEVEN W. LONGCOR, JOHN E. SANCHEZ, JR., LAWRENCE SCHLOSS, PHILIP F.S. SWAB, EDMOND WARD
  • Patent number: 8062942
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 22, 2011
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John E. Sanchez, Jr., Philip Swab
  • Patent number: 7889539
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: February 15, 2011
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe Chevallier, John E. Sanchez, Jr., Philip Swab
  • Patent number: 7701834
    Abstract: A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: April 20, 2010
    Inventors: Darrell Rinerson, Christophe Chevallier, John E. Sanchez, Jr., Lawerence Schloss
  • Patent number: 7633790
    Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: December 15, 2009
    Inventors: Darrel Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe J. Chevallier, John E. Sanchez, Jr., Philip Swab
  • Publication number: 20090303772
    Abstract: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 10, 2009
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Darrell Rinerson, Christophe Chevallier, Wayne Kinney, Roy Lambertson, John E. Sanchez, JR., Lawrence Schloss, Philip Swab, Edmond Ward
  • Patent number: 7394679
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: July 1, 2008
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe Chevallier, John E. Sanchez, Jr., Philip Swab
  • Patent number: 7326979
    Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: February 5, 2008
    Inventors: Darrell Rinerson, Wayne Kinney, John E. Sanchez, Jr., Steven W. Longcor, Steve Kuo-Ren Hsia, Edmond Ward, Christophe Chevallier
  • Patent number: 7082052
    Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: July 25, 2006
    Inventors: Darrell Rinerson, Wayne Kinney, Edmond Ward, Steve Kuo-Ren Hsia, Steven W. Longcor, Christophe Chevallier, John E. Sanchez, Jr., Philip Swab
  • Patent number: 6989604
    Abstract: An integrated circuit having a substrate and a semiconductor device thereon. A stop layer over the substrate has a first dielectric layer formed thereon having an opening into which a first conformal barrier is formed. A first conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the first conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the first dielectric layer. A conductor material is formed in the opening over the vertical portions of the first conformal barrier liner and the first stop layer.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: January 24, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christy Mei-Chu Woo, Minh Van Ngo, John E. Sanchez, Jr., Steven C. Avanzino
  • Patent number: 6972985
    Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: December 6, 2005
    Inventors: Darrell Rinerson, Christophe J. Chevallier, Philip F. S. Swab, Steve Kuo-Ren Hsia, John E. Sanchez, Jr., Steven W. Longcor
  • Patent number: 6836017
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: December 28, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Jr., Suzette K. Pangrle
  • Patent number: 6723635
    Abstract: Low-k ILDs are protected from degradation during damascene processing by depositing a thin, conformal silicon carbide liner with a silicon-rich surface before barrier metal layer deposition. Embodiments include forming a dual damascene opening in porous low-k dielectric layers, depositing a thin silicon carbide liner with a silicon-rich surface lining the opening, depositing a barrier metal layer, such as a Ta/TaN composite, and filling the opening with Cu.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: April 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Christy Mei-Chu Woo, Steven C. Avanzino, John E. Sanchez, Jr., Suzette K. Pangrle