Abstract: "Doorbelling" in a generating system including a fault detecting circuit is prevented without the use of auxiliary power supply for a generator control unit. The generating system includes a permanent magnet generator (14) driving an exciter winding (18) and a relay (26) is utilized for interconnecting the two. Control of the relay (26) is exercised by a microcomputer (32) including a non-volatile memory (48) and programmed to remember the occurrence of a fault and thereafter prevent the relay (26) from cyclically opening and closing in response to power changes occurring as a result of connection and disconnection of the exciter winding (18) from the permanent magnet generator (14).

Abstract: A frequency detector in a frequency control for a generating system includes a system processor and a counter for deriving a digital count proportional to the output frequency of the generating system. The system processor executes a series of control cycles during which the processor controls the speed at which the generating system is driven in accordance with the output frequency. The system processor detects the digital count at a predetermined point in each control cycle and resets the counter to initiate generation of a new digital count. The data from the detector does not require an interrupt handling procedure and hence complexity is minimized.

Abstract: A controller operable in a normal mode of operation to control an output device in response to a sensed condition includes means for detecting a fault in the controller or output device. Means are responsive to the fault detecting means for controlling the output device in a failsafe mode of operation wherein the output device is safely operated without regard to the sensed condition when a fault is detected. Means responsive to the fault detecting means causes a return to the normal mode of operation only if the existence of the fault can be detected while in the failsafe mode and the fault ceases to exist during such time.

Abstract: A data converter comprises a pair of NAND gates and a pair of bipolar differential operational amplifiers. Monopolar binary digital data in uninverted and inverted forms and a clock signal are connected with the NAND gate inputs. The NAND gate outputs are complementary monopolar data signals at the clock frequency and are cross-coupled to the direct and inverting inputs of the operational amplifiers. The outputs of the operational amplifiers are complementary bipolar data signals. Low pass filters establish the rise and fall times of the bipolar data signals and the high frequency response limit. Voltage buffers isolate the converter from the data transmission line and include current limiting resistors which prevent damage in the event of a short circuit of the line.