Abstract: A low power, high noise margin logic gate comprises: an input terminal, an output terminal, and first and second voltage supply terminals; an enhancement mode switching FET having a gate connected to the input terminal, a source and a drain; a load device connected between the drain of the switching FET and the first voltage supply terminal; a feedback device connected between the source of the switching FET and the second voltage supply terminal; a two terminal level shift device connected between the drain of the switching FET and the output terminal; and an enhancement mode pulldown FET having a gate connected to the source of the switching FET, a source connected to the second voltage supply terminal, and a drain connected to the output terminal. The logic gate as defined above operates as an invertor.

Abstract: A terminal of an integrated circuit is protected from electrostatic discharge voltages at the terminal by a protection circuit which includes a bidirectionally conductive transistor as a discharge current shunting device. A bidirectionally conductive controlled path is provided between the terminal and one of two voltage supply terminals. The transistor has a biassing resistor connected between the terminal and its control electrode. A normally reverse biassed diode is connected between the control electrode on another of the voltage supply terminals. For an n-channel FET or an npn bipolar transistor, when a positive electrostatic discharge is applied to the terminal, a current flowing through the biassing resistor turns on the transistor to provide a discharge path from the terminal to the voltage supply terminal.

Abstract: A GaAs D-MESFET logic system having a low power delay product has a switching second and a voltage level shifting section. The voltage level shifting section consists of a chain of diodes and a pulldown transistor. The switching section consists of an array of D-MESFETs which acts to speed up operation of a coupling capacitor. The low power dissipation of known capacitor coupled D-MESFET logic is thus preserved, while reducing gate delay.