Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later.

Abstract: An interconnection circuitry for two local area contention networks which is adapted to jam the respective networks when stations on both sides of the interconnection circuitry attempt transmission. If stations on opposite sides of the interconnect circuitry begin transmitting at the same time, the interconnect circuitry operates to place a high signal on the channel of each network and all stations will detect that the data is garbled and discard it.

Abstract: This disclosure relates to a line driver circuit for a station in a data transmission network, which driver circuit is adapted to drive the channel medium with a constant current so that conflicts or collisions with data transmissions from other stations will be cancelled out thereby preventing any particular station from dominating reception of a neighboring station. Each station is adapted to operate in a cyclic mode for contending for access to the network channel where a three-state cycle is employed, which states are the idle state, the packet-being-transmitted state and the acknowledgment period state. Each station will not begin transmission until it determines that the tunnel is in an idle state. Once the station has determined that the channel is idle, it will then delay for a period of time that is randomly chosen and, if the channel is still idle, will then begin transmission.

Abstract: This disclosure relates to a station for a data transmission network which is adapted to operate in a cyclic mode for contending for access to the network channel along with other stations of the network. The three states of the cycle are the idle state, the packet-being-transmitted state and the acknowlegement period state. Each station will not begin transmission until it determines that the channel is in an idle state. Once the station has determined that the channel is idle, it will then delay for a period of time that is randomly chosen and, if the channel is still idle, will then begin transmission. In this way, contention conflicts between stations is minimized without unduly restricting communication between stations. Following transmission, the channel will again be quiescent a short period of time before the acknowledgement signal is transmitted from the receiver.