Abstract: A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

Abstract: A method for initializing functional blocks on an electronic chip includes writing a programmable broadcast address to one or more functional blocks in a broadcast group; setting the one or more functional blocks in the broadcast group to a broadcast enable mode; writing one or more transactions to the programmable broadcast address; and disabling the broadcast enable mode.

Abstract: A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

Abstract: Example embodiments relate to response control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller, and an interface to a non-compliant memory technology that does not comply with the data transfer standard. The memory module may include a command monitoring circuit to determine whether a command from the memory controller has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard. The memory module may include an error causing circuit that signals to the memory controller or an operating system when the command has not or will not complete within the defined amount of time.

Abstract: An example apparatus has an interface to a first memory and to a second memory. The example apparatus also has a control logic that functions to control the interface. The control logic can control the interface to write a data word to the first memory and to write an error checking and correcting (ECC) word associated with the data word to the second memory.

Abstract: Two reference voltages and two differential receivers are used to detect low-to-high and high-to-low transitions on an input signal and set a received signal output. One reference voltage is set near but under the electrical high voltage level and the other is set near but above the electrical low voltage level. The reference voltage that is closest to the input signal is designated as the active reference voltage. When the input signal crosses the active reference voltage digital value of the received signal output is changed. When the input signal then crosses the inactive reference voltage, the inactive reference voltage is made the active reference voltage. A dead-time is then waited where input signal crossings of the active reference voltage are ignored. After the dead-time, input signal crossings of the active reference voltage will change the received signal output.

Abstract: Two reference voltages and two differential receivers are used to detect low-to-high and high-to-low transitions on an input signal and set a received signal output. On reference voltage is set near but under the electrical high voltage level and the other is set near but above the electrical low voltage level. The reference voltage that is closest to the input signal is designated as the active reference voltage. When the input signal crosses the active reference voltage digital value of the received signal output is changed. When the input signal then crosses the inactive reference voltage, the inactive reference voltage is made the active reference voltage. A dead-time is then waited where input signal crossings of the active reference voltage are ignored. After the dead-time, input signal crossings of the active reference voltage will change the received signal output.