Patents by Inventor John E. Turner

John E. Turner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11135110
    Abstract: A patient support apparatus includes a base frame, lift mechanism supporting an upper frame relative to the base frame, a load frame, and a plurality of deck sections, a patient support surface, and a number of barriers positioned about the patient supporting surface. The patient support apparatus includes a notification system for visually notifying a caregiver of a condition or status of a component of the patient support apparatus.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: October 5, 2021
    Assignee: Hill-Rom Services, Inc.
    Inventors: Robert M. Zerhusen, Richard H. Heimbrock, Arpit Shah, Aziz A. Bhai, Bradley T. Smith, Catherine M. Wagner, Charles A. Lachenbruch, Clay G. Owsley, Dan R. Tallent, Daniel Nachtigal, David L. Bedel, David J. Brzenchek, David J. Hitchcock, David P. Lubbers, Douglas A. Seim, Douglas E. Borgman, Eric D. Benz, Florin Iucha, Frank E. Sauser, Gavin M. Monson, James W. Pascoe, James L. Walke, Jared Rude, John G. Byers, John D. Christie, Jonathan D. Turner, Joshua A. Williams, Karen Lanning, Kathryn R. Smith, Kirsten M. Emmons, Mary Kay Brinkman, Michael Buccieri, Nathaniel W. Hixon, Neal Wiggermann, Richard J. Schuman, Sr., Scott M. Corbin, Sravan Mamidi, Todd P. O'Neal, Todd S. Ventrola, Travis Pelo, Unnati Ojha, John Goewert
  • Patent number: 7800405
    Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: September 21, 2010
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
  • Publication number: 20090267645
    Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
    Type: Application
    Filed: June 15, 2009
    Publication date: October 29, 2009
    Applicant: Altera Corporation
    Inventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
  • Patent number: 7557608
    Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: July 7, 2009
    Assignee: Altera Corporation
    Inventors: Andy L Lee, Wanli Chang, Cameron McClintock, John E Turner, Brian D Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G Cliff
  • Patent number: 7319253
    Abstract: A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: January 15, 2008
    Assignee: Altera Corporation
    Inventors: Lakhbeer S Sidhu, Irfan Rahim, Jeffrey Watt, John E Turner
  • Patent number: 7119574
    Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE?Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: October 10, 2006
    Assignee: Altera Corporation
    Inventors: Andy L Lee, Wanli Chang, Cameron McClintock, John E Turner, Brian D Johnson, Chiao Kai Hwang, Richard Y Chang, Richard G Cliff
  • Patent number: 6876572
    Abstract: Programmable logic devices are provided having configuration memory cells that exhibit decreased soft error rates. A stabilizing capacitor may be connected between each of the memory cell's input and output terminals. The capacitor may be a metal-insulator-metal capacitor formed using a vertical structure, a horizontal structure, or a hybrid vertical-horizontal structure. The memory cell may have inverter transistors of increased strength to help stabilize the memory cell.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: April 5, 2005
    Assignee: Altera Corporation
    Inventor: John E. Turner
  • Patent number: 6828620
    Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: December 7, 2004
    Assignee: Altera Corporation
    Inventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
  • Publication number: 20040233701
    Abstract: Programmable logic devices are provided having configuration memory cells that exhibit decreased soft error rates. A stabilizing capacitor may be connected between each of the memory cell's input and output terminals. The capacitor may be a metal-insulator-metal capacitor formed using a vertical structure, a horizontal structure, or a hybrid vertical-horizontal structure. The memory cell may have inverter transistors of increased strength to help stabilize the memory cell.
    Type: Application
    Filed: May 21, 2003
    Publication date: November 25, 2004
    Applicant: Altera Corporation
    Inventor: John E. Turner
  • Patent number: 6724222
    Abstract: A technique and circuitry interfaces a programmable logic integrated circuit compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, an on-chip voltage less than the external supply level of the programmable logic integrated circuit is provided to a core portion of a programmable logic integrated circuit by way of a conversion transistor. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. Externally, the programmable logic integrated circuit will interface with an external supply voltage level. The input and output signals to and from the programmable logic integrated circuit will be compatible with the external supply level.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: April 20, 2004
    Assignee: Altera Corporation
    Inventors: Rakesh H. Patel, John E. Turner, John D. Lam, Wilson Wong
  • Publication number: 20040000999
    Abstract: A system and method for scanning carriers for objects include the capability to sense a radioactive object in the detection proximity of a platform and form a signal indicative thereof and to determine whether an illicit radioactive object may be in the detection proximity. The system and method also include the capability to sense a metallic object in the detection proximity of the platform and form a signal indicative thereof and to determine whether an illicit metallic object may be in the detection proximity.
    Type: Application
    Filed: November 8, 2002
    Publication date: January 1, 2004
    Inventors: John E. Turner, Brian J. Turner, David F. Turner, Robert M. Turner, Charles Gorbet, Mitchell M. Truitt, Les R. Burk
  • Patent number: 6661253
    Abstract: Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: December 9, 2003
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Wanli Chang, Cameron McClintock, John E. Turner, Brian D. Johnson, Chiao Kai Hwang, Richard Yen-Hsiang Chang, Richard G. Cliff
  • Publication number: 20030197218
    Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
    Type: Application
    Filed: May 12, 2003
    Publication date: October 23, 2003
    Applicant: Altera Corporation
    Inventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
  • Patent number: 6604228
    Abstract: A technique of fabricating an integrated circuit adaptable for use in various operating voltage environments. The same integrated circuit design may be used in different operating modes depending on the particular option selected. For example, there may be three options (710, 715, 720). The various options of the integrated circuit formed on the same integrated circuit. During the fabrication of the integrated circuit, the desired option is selected. This may be accomplished, for example, by selecting the appropriate metal masks (725). Other techniques include, to name a few, using programmable links, programmable fuses, programmable cells, and many others. The technique of the present invention reduces the costs of integrated circuits. The same design may be used for a variety of purposes and in a variety of voltage environments without needing to develop and design a specific integrated circuit for each voltage condition.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: August 5, 2003
    Assignee: Altera Corporation
    Inventors: Rakesh H. Patel, John E. Turner
  • Publication number: 20030137420
    Abstract: A system and method for scanning individuals for illicit objects include the ability to scan a wheeled user transport device and an individual being transported thereby for metallic objects and to determine whether an illicit object may be present, without activating an alarm for the user transport device while detecting illicit objects on the individual.
    Type: Application
    Filed: October 10, 2002
    Publication date: July 24, 2003
    Applicant: Ranger Security Detectors, Inc.
    Inventors: John E. Turner, Brian J. Turner, Les R. Burk
  • Publication number: 20030117174
    Abstract: A technique provides an on-chip voltage to a core portion of a programmable logic integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.
    Type: Application
    Filed: February 13, 2003
    Publication date: June 26, 2003
    Applicant: Altera Corporation, a corporation of Delaware
    Inventors: Rakesh H. Patel, John E. Turner, John D. Lam, Wilson Wong
  • Patent number: 6583646
    Abstract: An input/output driver for interfacing directly with a voltage at a pad which is above a supply voltage for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator for preventing leakage current paths.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: June 24, 2003
    Assignee: Altera Corporation
    Inventors: Rakesh H. Patel, John E. Turner, Wilson Wong
  • Patent number: 6573138
    Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: June 3, 2003
    Assignee: Altera Corporation
    Inventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
  • Patent number: 6563343
    Abstract: A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: May 13, 2003
    Assignee: Altera Corporation
    Inventors: Rakesh H. Patel, John E. Turner, John D. Lam, Wilson Wong
  • Patent number: 6472903
    Abstract: In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and—to the extent that each such scheme requires a reference voltage—the same reference voltage requirements.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: October 29, 2002
    Assignee: Altera Corporation
    Inventors: Kerry Veenstra, Krishna Rangasayee, John E. Turner