Patents by Inventor John E. Twomey

John E. Twomey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tracing instruction flow in an integrated processor
    Patent number: 7340564
    Abstract: Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: March 4, 2008
    Assignee: Broadcom Corporation
    Inventor: John E. Twomey
  • System on a chip for network storage devices
    Patent number: 7246245
    Abstract: In one embodiment, an apparatus includes a first integrated processor, a second integrated processor, and a security processor. The first integrated processor has one or more network interfaces for receiving packets and also has a second interface. The second integrated processor is coupled to the second interface. A security processor is coupled to the second integrated processor. Also, a storage switch is contemplated employing one or more line cards which include the apparatus. The storage switch further includes at least one switch fabric card coupled to the at least one line card, wherein the switch fabric card is configured to route packets from the at least one line card and from one or more storage devices on a switch fabric. In another embodiment, the integrated processors may be systems on a chip (SOCs).
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: July 17, 2007
    Assignee: Broadcom Corporation
    Inventor: John E. Twomey
  • System on a chip for network storage devices
    Publication number: 20030131228
    Abstract: In one embodiment, an apparatus includes a first integrated processor, a second integrated processor, and a security processor. The first integrated processor has one or more network interfaces for receiving packets and also has a second interface. The second integrated processor is coupled to the second interface. A security processor is coupled to the second integrated processor. Also, a storage switch is contemplated employing one or more line cards which include the apparatus. The storage switch further includes at least one switch fabric card coupled to the at least one line card, wherein the switch fabric card is configured to route packets from the at least one line card and from one or more storage devices on a switch fabric. In another embodiment, the integrated processors may be systems on a chip (SOCs).
    Type: Application
    Filed: April 1, 2002
    Publication date: July 10, 2003
    Inventor: John E. Twomey