Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

Abstract: A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

Abstract: A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

Abstract: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

Abstract: Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.

Abstract: A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

Abstract: A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

Abstract: A system and method for synchronizing a strobed memory system 10. During memory read and/or memory write operations the corresponding data strobe is sampled at the data destination 50/55 according to a local clock signal 71/73. Based on the results of the sampling, the data strobe and local clock signal are synchronized. In this manner, the data is synchronized to the local clock signal so that sampling of data at the data destination can be performed according to the local clock signal rather than the data strobe.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.