Abstract: A device controller interfaced between an electronic processing device and a sector-based data storage device, includes a processor connected to a clock, and a computer memory having a control list stored therein. A control list includes a security feature entry having a target sector range, time data associated with the target sector range, and at least one security response associated with the target sector range. The processor determines, based at least in part on interrogation of the control list and a clock time, the time data of the entry conflicts with the clock time, and executes the at least one security response.

Abstract: A device controller interfaced between an electronic processing device and a sector-based data storage device, includes a processor connected to a clock, and a computer memory having a control list stored therein. A control list includes a security feature entry having a high level data characteristic, time data associated with the characteristic, and at least one security response associated with the characteristic. The processor determines, based at least in part on interrogation of the control list and a clock time, the time data of the entry conflicts with the clock time, and executes the at least one security response.

Abstract: A device controller interfaced between an electronic processing device and a sector-based data storage device, includes a processor connected to a clock, and a computer memory having a control list stored therein. A control list includes a security feature entry having a target sector range, time data associated with the target sector range, and at least one security response associated with the target sector range. The processor determines, based at least in part on interrogation of the control list and a clock time, the time data of the entry conflicts with the clock time, and executes the at least one security response.

Abstract: A device controller interfaced between an electronic processing device and a sector-based data storage device, includes a processor connected to a clock, and a computer memory having a control list stored therein. A control list including a security feature entry including a target sector range, time data associated with the target sector range, and at least one security response associated with the target sector range. The processor determines, based at least in part on interrogation of the control list and a clock time, the time data of the entry conflicts with the clock time, and executes the at least one security response. Time data can represent an expiration date or a time window, with a conflict arising if the clock time is beyond the expiration date or within the time window, respectively.

Abstract: A device controller interfaced between an electronic processing device and a sector-based data storage device, includes a processor connected to a clock, and a computer memory having a control list stored therein. A control list including a security feature entry including a target sector range, time data associated with the target sector range, and at least one security response associated with the target sector range. The processor determines, based at least in part on interrogation of the control list and a clock time, the time data of the entry conflicts with the clock time, and executes the at least one security response. Time data can represent an expiration date or a time window, with a conflict arising if the clock time is beyond the expiration date or within the time window, respectively.

Abstract: A device controller and method to forensically secure a storage device. A device controller, interfaced between a processing device and a storage device, includes a processor and computer memory having stored therein a maintenance list including a maintenance routine. In response to a forensic mode request from the processing device, the processor transitions the device controller to a forensic mode that disables execution of the maintenance routine and any write requests involving the storage device. In response to a subsequent forensic mode request, the processor returns the device controller to a free mode. Transitioning and/or returning can be conditioned on authentication of any one or more forensic mode requests.