Abstract: A microcavity structure and a method for forming an integrated circuit device including a microcavity structure is disclosed. This invention includes a layer or substrate having a topography such as a pair of raised features. A void forming material, such as a Boro-Phosphorus Silicate Glass (BPSG) is deposited on the substrate such that a void is formed therein. A pinning material having a relatively greater density than the void forming material is deposited over the void forming material. The materials are then annealed by a process such as Rapid Thermal Anneal (RTA). The materials are then polished, by for example, Chemical Mechanical Polishing (CMP) to expose the top of the void. The void is then etched using an anisotropic etch, such as Reactive Ion Etch (RIE) to remove the void forming material. The method may be used to provide self-aligned contact vias.

Abstract: Machine structures each comprising a stack of a plurality of micromachine layers laminated together are presented, along with fabrication methods therefore. Each machine structure includes a movable member(s) defined from microstructure of at least one layer of the plurality of micromachine layers comprising the stack. During fabrication, the micromachine layers are separately formed using VLSI techniques and then subsequently laminated together in a selected arrangement in the stack to define the machine structure.

Abstract: An integrated circuit structure, such as a stackable integrated circuit chip, having at least one face. The structure comprises at least one elongate conductor running therein and terminating in a contact section having an exposed end at the at least at one face of the structure. At least one face conductor forms an electrical interface with the exposed end of the contact section. Means for limiting electromigration about the electrical interface, such as a contact section of the conductor having a cross-sectional area greater then a nominal-sectional area of the conductor, are disclosed.

Abstract: The present invention provides a conductive structure for use in semiconductor devices. The structure can be used to interconnect the various diffusion regions or electrodes of devices formed on a processed semiconductor substrate to a layer of metal, to interconnect overlying layers of metal or to provide the gate electrode of an FET device formed on the surface of a semiconductor substrate. Various embodiments of the invention are described, but in broad form the active metallurgy of the present invention comprises a thin continuous layer to titanium--titanium nitride and a thick layer of a refractory metal, e.g. tungsten, overlying the titanium nitride layer.

Abstract: A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through these defects is thereby diminished. The method also provides self-alignment of the lines and contact holes for subsequent formation of stud via connections through which contact is desired to underlying metallization levels. Deposition of a conformal sacrificial material film fills the small, undesired sublithographic contact hole image formed and covers both mask surfaces through which the misaligned line image and contact opening were etched. Isotropic etching removes the conformal layer from all planar surfaces except those of the undesired sublithographic contact hole image.

Abstract: A device and method are described for defining a region on a wall of a semiconductor structure, such as a sidewall of a trench formed in a semiconductor substrate. The method includes the steps of forming a vertical structure above the semiconductor structure and spaced parallel to the wall; providing within the vertical structure an area of one of transparence, reflection or refraction; and projecting light at a given angle to the wall, wherein only a portion of the light passes the vertical structure via the area provided therein to impinge upon the wall of the semiconductor structure, and thereby define the region on the wall. As an alternative, the area can comprise an aperture in the vertical structure such that the vertical structure can be employed as a mask to direct selective ion implantation of the wall.

Abstract: An integrated circuit capacitor device that increases capacitance without proportionately using more substrate surface area. Uniquely, the capacitor uses up to all four sides of the first charge plate to store charge by surrounding it with a second charge plate with an insulator layer separating the two plates.

Abstract: A semiconductor device has an on-board decoupling capacitor provided at its interconnect region. The decoupling capacitor comprises two layers of metallurgy separated by a dielectric layer wherein two of the layers are identically patterned.

Abstract: A chemical mechanical planarization tool and method are presented employing a non-linear motion of the carrier arm relative to the polishing pad. The non-linear motion of the carrier arm relative to the polishing pad can be accomplished in a variety of ways, for example, employing a mechanical template having an irregular opening or programming the carrier displacement mechanism to move the carrier in an irregular, non-rotational X-Y path over the polishing pad.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: Methods for alignment of stacked integrated circuit chips and the resultant three-dimensional semiconductor structures. A thickness control layer is deposited, as needed, on each integrated circuit chip. The thickness of the layer is determined by the thickness of the chip following a grind stage in the fabrication process. Complementary patterns are etched into the thickness control layer of each chip and into adjacent chips. Upon stacking the chips in a three dimensional structure, precise alignment is obtained for interconnect pads which are disposed on the edges of each integrated circuit chip. Dense bus and I/O networks can be thereby supported on a face of the resultant three-dimensional structure.

Abstract: Semiconductor structures and associated methods for limiting electromigration at wiring interfaces. Increased cross-sectional contact sections are employed, with conducting studs in contact therewith. Methods for fabrication and use are disclosed. Contacts for stackable integrated circuit chips and three-dimensional electronic modules particularly are modified with the disclosed structures and methods.

Abstract: Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.

Abstract: A semiconductor structure comprising two gate stacks of equal height but different composition. The two gate stacks each comprise two layers, with the first layer of each gate stack comprising the same material and the second layer of each gate stack comprising a different material. Each gate stack has an upper surface a distance `X` above the upper planar surface of a substrate of the semiconductor structure. Thus, the two gate stacks of different composition are of identical height.

Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.

Abstract: A semiconductor device has an on-board decoupling capacitor provided at its interconnect region. The decoupling capacitor comprises two layers of metallurgy separated by a dielectric layer wherein two of the layers are identically patterned.

Abstract: A device and method are described for defining a region on a wall of a semiconductor structure, such as a sidewall of a trench formed in a semiconductor substrate. The method includes the steps of forming a vertical structure above the semiconductor structure and spaced parallel to the wall; providing within the vertical structure an area of one of transparence, reflection or refraction; and projecting light at a given angle to the wall, wherein only a portion of the light passes the vertical structure via the area provided therein to impinge upon the wall of the semiconductor structure, and thereby define the region on the wall. As an alternative, the area can comprise an aperture in the vertical structure such that the vertical structure can be employed as a mask to direct selective ion implantation of the wall.

Abstract: A chimney capacitor is formed having two plates, of which each is disposed above and contacts a corresponding electrical contact. The electrical contacts facilitate electrical access to the plates of the chimney capacitor. One of the electrical contacts may comprise part of a general wiring layer that may be used for both electrically accessing the capacitor and for general wiring within the IC chip. Formation of the chimney capacitor proceeds by first forming two electrical contacts on an integrated circuit ("IC") chip. A planar insulating layer is formed thereover, and the capacitor is formed at least partially within the planar insulating layer such that each plate is electrically connected to a corresponding electrical contact.

Abstract: An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.