Abstract: A high precision DAC (10) incorporates a low precision DAC (18) and current sources (15(A)-15(O)) whose full-scale currents are adjusted to match a reference current generated by an analog calibration circuit (28). An additional low precision DAC (20) and another current source (16) are spares that allow periodic calibration of the high precision DAC (10) to occur in the background without taking the high precision DAC (10) off-line or out of service. A thermometer code generated by a thermometer code circuit (12) is used by a thermometer mapper circuit (13) to enable the most recently calibrated current sources to generate currents having the highest probability for use by the high precision DAC (10).

Abstract: A temperature compensated low voltage reference that produces an output voltage less than the silicon band-gap voltage. The low voltage reference includes at least a first and a second transistor for providing a voltage independent of variations in the collector power supply and at least a third transistor for developing a voltage that is a fractional value of the base-to-emitter voltage drop of a transistor. The at least a third transistor for developing is coupled with the at least a first and a second transistor for providing. The low voltage reference also includes an output transistor for providing an output voltage. The output transistor is controlled by the voltage provided by the at least a first and a second transistor for providing so that the output voltage is essentially insensitive to temperature variations and is a lower value than the silicon band-gap voltage.

Abstract: An amplifier configuration is disclosed which utilizes a resistive, positive feedback network to develop a high input impedance. The amplifier, which is suitable for manufacture in monolithic integrated circuit form, includes a pair of differential transistors which are coupled to a current supply that provides a current having a predetermined temperature coefficient. A resistor, which is connected between the emitters of the differential transistors, develops either a temperature stable offset voltage or an offset voltage having a desired temperature coefficient in response to the current. A negative feedback circuit facilitates control of the bias voltages for the pair of differential transistors. Temperature stable quiescent input and output voltage levels are derived from the offset voltage through the feedback network.