Patents by Inventor John Edward Sheets, II
John Edward Sheets, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8754417Abstract: Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.Type: GrantFiled: September 10, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, Phil Christopher Felice Paone, David Paul Paulsen, John Edward Sheets, II
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Patent number: 8574982Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.Type: GrantFiled: February 25, 2010Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams
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Patent number: 8535393Abstract: A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.Type: GrantFiled: January 4, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, John Edward Sheets, II, Trevor Joseph Timpane
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Patent number: 8536632Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.Type: GrantFiled: February 14, 2012Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Louis L. Hsu, Jack A. Mandelman, John Edward Sheets, II
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Patent number: 8536587Abstract: A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.Type: GrantFiled: January 3, 2011Date of Patent: September 17, 2013Assignee: International Business Machines CorporationInventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, John Edward Sheets, II, Trevor Joseph Timpane
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Patent number: 8518767Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.Type: GrantFiled: February 28, 2007Date of Patent: August 27, 2013Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman, John Edward Sheets, II
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Publication number: 20130001701Abstract: Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd Alan Christensen, Phil Christopher Felice Paone, David Paul Paulsen, John Edward Sheets, II
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Patent number: 8314001Abstract: Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.Type: GrantFiled: April 9, 2010Date of Patent: November 20, 2012Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, Phil Christopher Felice Paone, David Paul Paulsen, John Edward Sheets, II
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Patent number: 8300450Abstract: A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.Type: GrantFiled: November 3, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, John Edwards Sheets, II
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Publication number: 20120146112Abstract: Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure.Type: ApplicationFiled: February 14, 2012Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman, John Edward Sheets, II
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Publication number: 20120106235Abstract: A method and embedded dynamic random access memory (EDRAM) circuit for implementing a physically unclonable function (PUF), and a design structure on which the subject circuit resides are provided. An embedded dynamic random access memory (EDRAM) circuit includes a first EDRAM memory cell including a memory cell true storage capacitor and a second EDRAM memory cell including a memory cell complement storage capacitor. The memory cell true storage capacitor and the memory cell complement storage capacitor include, for example, trench capacitors or metal insulator metal capacitors (MIM caps). A random variation of memory cell capacitance is used to implement the physically unclonable function. Each memory cell is connected to differential inputs to a sense amplifier. The first and second EDRAM memory cells are written to zero and then the first and second EDRAM memory cells are differentially sensed and the difference is amplified to consistently read the same random data.Type: ApplicationFiled: November 3, 2010Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd Alan Christensen, John Edwards Sheets, II
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Patent number: 8138054Abstract: An enhanced FET capable of controlling current above and below a gate of the FET. The FET is formed on a semiconductor substrate. A source and drain are formed in the substrate (or in a well in the substrate). A first epitaxial layer of similar doping to the source and drain are grown on the source and drain, the first epitaxial layer is thicker than the gate, but not so thick as to cover the top of the gate. A second epitaxial layer of opposite doping is grown on the first epitaxial layer thick enough to cover the top of the gate. The portion of the second epitaxial layer above the gate serves as a body through which the gate controls current flow between portions of the first epitaxial layer over the drain and the source.Type: GrantFiled: April 1, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: David Howard Allen, Todd Alan Christensen, David Paul Paulsen, John Edward Sheets, II
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Patent number: 8105940Abstract: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.Type: GrantFiled: February 10, 2010Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, John Edward Sheets, II
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Patent number: 8079134Abstract: A method is provided that utilizes silicon through via technology, to build a Toroid into the chip with the addition of a layer of magnetic material such as Nickel above and below the T-coil stacked multi-ring structure. This allows the connection between the inner via and an array of outer vias. This material is added on a BEOL metal layer or as an external coating on the finished silicon. Depending on the configuration and material used for the via, the inductance will increase approximately two orders of magnitude (e.g., by utilizing a nickel via core). Moreover, a ferrite material with proper thermal conduction properties is used in one embodiment.Type: GrantFiled: August 1, 2008Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Andrew Benson Maki, Gerald Keith Bartley, Philip Raymond Germann, Mark Owen Maxson, Darryl John Becker, Paul Eric Dahlen, John Edward Sheets, II
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Publication number: 20110248349Abstract: Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.Type: ApplicationFiled: April 9, 2010Publication date: October 13, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Todd Alan Christensen, Phil Christopher Felice Paone, David Paul Paulsen, John Edward Sheets, II
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Publication number: 20110204428Abstract: A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM.Type: ApplicationFiled: February 25, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl Robert Erickson, David Paul Paulsen, John Edward Sheets, II, Kelly L. Williams
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Patent number: 7989918Abstract: A method and tamper detection circuit for implementing tamper and anti-reverse engineering evident detection in a semiconductor chip, and a design structure on which the subject circuit resides are provided. A capacitor is formed with the semiconductor chip including the circuitry to be protected. A change in the capacitor value results responsive to the semiconductor chip being thinned, which is detected and a tamper-detected signal is generated.Type: GrantFiled: January 26, 2009Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Todd Alan Christensen, Paul Eric Dahlen, John Edward Sheets, II
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Patent number: 7935629Abstract: An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.Type: GrantFiled: October 22, 2007Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper, John Edward Sheets, II
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Patent number: 7935546Abstract: A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.Type: GrantFiled: February 6, 2008Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, John Edward Sheets, II, Trevor Joseph Timpane
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Publication number: 20110096310Abstract: A method, structure, system of aligning a substrate to a photomask. The method includes: directing incident light through a pattern of clear regions transparent to the incident light in an opaque-to-the-incident-light region of a photomask, through a lens and onto a photodiode formed in a substrate, the photodiodes electrically connected to a light emitting diode formed in the substrate, the light emitting diode emitting light of different wavelength than a wavelength of the incident lights; measuring an intensity of emitted light from light emitting diode; and adjusting alignment of the photomask to the substrate based on the measured intensity of emitted light.Type: ApplicationFiled: January 3, 2011Publication date: April 28, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Axel Aguado Granados, Benjamin Aaron Fox, Nathaniel James Gibbs, Andrew Benson Maki, John Edward Sheets, II, Trevor Joseph Timpane