Patents by Inventor John Edward Vincent
John Edward Vincent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11599469Abstract: A computer system includes a first core including a first local cache and a second core including a second local cache. The first core and the second core are coupled through a remote link. A shared cache coupled to the first core and to the second core. The shared cache includes an ownership table that includes a plurality of entries indicating if a cache line is stored solely in the first local cache or solely in the second local cache. The remote link includes a first link between the first core and the shared cache and a second link between the second core and the shared cache.Type: GrantFiled: January 7, 2022Date of Patent: March 7, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Louis-Philippe Hamelin, Chang Hoon Lee, John Edward Vincent, Olivier D'Arcy, Guy-Armand Kamendje Tchokobou
-
Publication number: 20220100575Abstract: Method and apparatus for process accelerator (PA) using configurable hardware accelerators is provided. The PA can include a plurality of processing elements (PEs). The PEs of the PA can be used to accelerate a process and/or one or more threads. PEs can include PE local memory which due to the memories' close physical proximity to the PE can result in reduced energy consumption. The plurality of PEs can be daisy-chain connected or DMA mode can be used to write the result of a PE directly into the PE local memory of another PE for further processing.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Chang Hoon LEE, Paul ALEPIN, John Edward VINCENT
-
Patent number: 11275590Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.Type: GrantFiled: March 11, 2016Date of Patent: March 15, 2022Assignee: Huawei Technologies Co., Ltd.Inventors: John Edward Vincent, Peter Man Kin Sinn, Benton Watson
-
Patent number: 10853077Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker circuit having a plurality of credit units associated with corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, and a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for a given period of time after the positive determination.Type: GrantFiled: January 25, 2016Date of Patent: December 1, 2020Assignee: Huawei Technologies Co., Ltd.Inventors: Louis-Philippe Hamelin, Peter Man-Kin Sinn, Chang Lee, Paul Alepin, Guy-Armand Kamendje Ichokobou, Olivier D'Arcy, John Edward Vincent
-
Patent number: 10761560Abstract: The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.Type: GrantFiled: October 15, 2018Date of Patent: September 1, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Chang Hoon Lee, John Edward Vincent, Louis-Philippe Hamelin, Paul Alepin
-
Publication number: 20200117231Abstract: The embodiments employ a transaction based design methodology to supply clocking when clock pulses are requested. The transactional module receives a clock when it requests a clock pulse and one stage of a logic pipeline is clocked at a time. This methodology reduces dynamic power dissipation by the transactional module from the dynamic power dissipated by traditional synchronous logic designs.Type: ApplicationFiled: October 15, 2018Publication date: April 16, 2020Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Chang Hoon LEE, John Edward VINCENT, Louis-Philippe HAMELIN, Paul ALEPIN
-
Publication number: 20170060579Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.Type: ApplicationFiled: March 11, 2016Publication date: March 2, 2017Inventors: John Edward VINCENT, Peter Man Kin SINN, Benton WATSON
-
Publication number: 20170060583Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker having a plurality of credit units associated to corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include: performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching a corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for given period of time after the positive determination.Type: ApplicationFiled: January 25, 2016Publication date: March 2, 2017Inventors: LOUIS-PHILIPPE HAMELIN, PETER MAN-KIN SINN, CHANG LEE, PAUL ALEPIN, GUY-ARMAND KAMENDJE TCHOKOBOU, OLIVIER DARCY, JOHN EDWARD VINCENT
-
Patent number: 6643285Abstract: A packet switch has a switching unit (SU) for switching packets between network links and a computing unit (CU) connected to the SU through a network link for implementing software control functions over the SU. The SU is formed of different functional components interconnected by generic buses. The components communicate with one another using program data units (PDUs) that are formatted and transmitted according to a shared device protocol. The communication between the components occurs by placing PDUs in bus frames that are passed from component to component. Information is exchanged between the components by adding information to or dropping information from the fields of the PDUs, or by concatenating new fields to the PDUs, as the frames pass from component to component. By using a generic bus to implement PDU-based interconnections within the SU, all the components are forced to support a common interface.Type: GrantFiled: February 17, 1998Date of Patent: November 4, 2003Assignee: Nortel Networks LimitedInventors: John Edward Vincent, George F. Irwin, Gary M. Depelteau, Tony Huang, David A. Fisher, James L. Watchorn, Melhem I. Chaar
-
Patent number: 6438132Abstract: A virtual port scheduler is provided optionally for inclusion as part of a partitioned packet scheduler comprising a queue manager. The virtual port scheduler maintains a plurality of statuses for remote ports which do not have their own scheduling functionality. On the basis of those statuses, the virtual port scheduler determines which virtual port to service next.Type: GrantFiled: October 14, 1998Date of Patent: August 20, 2002Assignee: Nortel Networks LimitedInventors: John Edward Vincent, James Leslie Watchorn
-
Patent number: 6404767Abstract: Systems and methods for implementing ABR (available bit rate) flow control in ATM (asynchronous transfer mode switches are provided. A partitioned architecture a featuring standalone ABR processing subsystem advantageously allows components to be changed with little impact on the switch's overal design. Both end-to-end and VS/VD (virtual source/virtual destination) flow control systems are provided as are both configurations for switches which are either standalone or connected to a switching fabric.Type: GrantFiled: June 17, 1998Date of Patent: June 11, 2002Assignee: Nortel Networks CorporationInventors: Gary Michael Depelteau, John Edward Vincent
-
Patent number: 6359884Abstract: A partitioned packet scheduler comprising a queue manager, an optionally connected rate shaper, and an optionally connected virtual port scheduler is provided. The packet scheduler is for use in a packet switch and has a very simple interface with the remainder of the switch consisting a channel for communicating buffer addresses and internal connection numbers. Very simple interfaces also exist between the queue manager and the rate shaper/virtual port scheduler thereby allowing independent design and update of these components to be performed.Type: GrantFiled: June 26, 1998Date of Patent: March 19, 2002Assignee: Nortel Networks LimitedInventor: John Edward Vincent
-
Patent number: 6262985Abstract: Methods and apparatus are described for translating identifiers that are used by computers to reference various entities such as data structures, external objects, or connections in a telecommunications network, from a bulkier less manageable format to a smaller more manageable format. Such translations are carried out to reduce the needless processing and memory demands that are made of a localized set of components when the large identifiers the set receives from other components include fields that none of the members of the set need to access. The invention is centerd around a two-stage look-up method wherein an inputted external identifier is divided into two parts. The first part of the inputted external identifier is used as an address into a first look-up table that contains base-addresses of a second look-up table. The second part of the inputted external identifier is used as an offset-address into the second look-up table.Type: GrantFiled: March 30, 1998Date of Patent: July 17, 2001Assignee: Nortel Networks LimitedInventors: Tony Huang, John Edward Vincent, James Leslie Watchorn, Paul Fong-Yan Hung, Osama Bahgat, Gary Depelteau, James McLaughlin
-
Patent number: 6118764Abstract: A system and method for updating the congestion indication and no increase values in an resource management cell on an available bit rate connection in an asynchronous transfer mode network. The method determines a per port elastic allocatable rate as a function of a port's capacity, and the current high priority traffic rate. The values are set according to the underutilization or over utilization of the allocated elastic bandwidth.Type: GrantFiled: December 30, 1997Date of Patent: September 12, 2000Assignee: Nortel Networks CorporationInventors: Gary Michael Depelteau, John Edward Vincent, Abdulaziz Almulhem
-
Patent number: 6115359Abstract: A system and method for updating the explicit rate in an resource management cell on an available bit rate connection in an asynchronous transfer mode network. The method determines a per port elastic allocatable rate as a function of a port's capacity, and the current high priority traffic rate. A steering factor is used which is iteratively increased or decreased according to the underutilization or over utilization of the allocated elastic bandwidth.Type: GrantFiled: December 30, 1997Date of Patent: September 5, 2000Assignee: Nortel Networks CorporationInventors: Gary Michael Depelteau, John Edward Vincent, Abdulaziz Almulhem