Patents by Inventor John Egler

John Egler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11693582
    Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: July 4, 2023
    Assignee: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Ali Khakifirooz, Camila Jaramillo, John Egler, Netra Mahuli, Renjie Chen, Yogesh Wakchaure
  • Publication number: 20220262431
    Abstract: Systems, apparatuses, and methods provide for technology for distinguishing an erased state, a first pass programmed state, and a second pass programmed state of a memory page. A threshold voltage state verify sense is performed. A memory page status is determined based on the threshold voltage state verify sense. The memory page status is one of erased, programmed with first pass data, and programmed with second pass data based on the threshold voltage state verify sense. A program continuation is performed after a program interruption based on the memory page status.
    Type: Application
    Filed: May 5, 2022
    Publication date: August 18, 2022
    Inventors: Sagar Upadhyay, Aliasgar S. Madraswala, John Egler
  • Publication number: 20220043596
    Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.
    Type: Application
    Filed: August 7, 2020
    Publication date: February 10, 2022
    Applicant: Intel Corporation
    Inventors: Aliasgar S. Madraswala, Ali Khakifirooz, Camila Jaramillo, John Egler, Netra Mahuli, Renjie Chen, Yogesh Wakchaure
  • Patent number: 7936610
    Abstract: Methods and systems to selectively refresh a single bit per cell non-volatile memory cell to reduce memory cell errors. In an embodiment, a memory device scans its memory cells, performing a multi-level read on memory cells in a single bit per cell mode. Depending on the state sensed, the cell is refreshed to a correct state if necessary. In one embodiment, the memory scan is appended to a user erase operation, a flash block is swapped with another bock if the state sensed indicates charge gain, and a flash cell is programmed up if the state sensed indicates charge loss.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Robert Melcher, Sean Eilert, John Egler