Patents by Inventor John F. Blecha, Jr.

John F. Blecha, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test interface for a digital circuit
    Patent number: 5426649
    Abstract: A test interface is disclosed that is added to a digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: June 20, 1995
    Assignee: AG Communication Systems Corporation
    Inventor: John F. Blecha, Jr.
  • Arrangement for testing digital circuit devices having tri-state outputs
    Patent number: 5166937
    Abstract: An arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
    Type: Grant
    Filed: December 26, 1990
    Date of Patent: November 24, 1992
    Assignee: AG Communication System Corporation
    Inventor: John F. Blecha, Jr.
  • Arrangement for testing digital circuit devices having bidirectional outputs
    Patent number: 5155733
    Abstract: An arrangement is disclosed that is added to digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
    Type: Grant
    Filed: December 26, 1990
    Date of Patent: October 13, 1992
    Assignee: AG Communication Systems Corporation
    Inventor: John F. Blecha, Jr.