Patents by Inventor John F. Bulzacchelli
John F. Bulzacchelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9467313Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: GrantFiled: June 22, 2015Date of Patent: October 11, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Patent number: 9444437Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.Type: GrantFiled: March 27, 2015Date of Patent: September 13, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John F. Bulzacchelli, Byungsub Kim
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Patent number: 9369263Abstract: Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal.Type: GrantFiled: June 30, 2015Date of Patent: June 14, 2016Assignee: International Business Machines CorporationInventors: Matthew B. Baecher, John F. Bulzacchelli, John F. Ewen, Gautam Gangasani, Mounir Meghelli, I, Matthew J. Paschal, Trushil N. Shah
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Patent number: 9335370Abstract: Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.Type: GrantFiled: January 16, 2014Date of Patent: May 10, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Eugene Atwood, Matthew B. Baecher, John F. Bulzacchelli, Stanislav Polonsky
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Patent number: 9288085Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: GrantFiled: March 26, 2015Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Patent number: 9231796Abstract: Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.Type: GrantFiled: November 25, 2013Date of Patent: January 5, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: John F. Bulzacchelli, Hayden C. Cranford, Jr., Daniel M. Dreps, David W. Siljenberg
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Publication number: 20150312064Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: ApplicationFiled: June 22, 2015Publication date: October 29, 2015Inventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Publication number: 20150295736Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.Type: ApplicationFiled: March 26, 2015Publication date: October 15, 2015Inventors: John F. Bulzacchelli, Pier Andrea Francese, Yong Liu, Thomas H. Toifl
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Publication number: 20150256160Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.Type: ApplicationFiled: May 20, 2015Publication date: September 10, 2015Inventors: JOHN F. BULZACCHELLI, BYUNGSUB KIM
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Publication number: 20150198647Abstract: Apparatus, method and computer program product for determining presence and relative magnitudes of on-chip AC coupling capacitors in a high-speed differential receiver device. A BIST method is employed to ultimately produce a dock count proportional to the fall time of a capacitor, and in the case of differential capacitors a difference in count values. Each capacitor path has a controllable first DAC current or voltage source. A second DAC current or voltage source, later in the data path and isolated from the capacitor node(s), is controlled to offset the voltage contribution of the charged and discharging capacitor. A count is recorded, starting when a capacitor charging current is shut off, and ends (the count) when the voltage of the charged capacitor falls below a threshold. A difference in count between the two data path capacitors is calculated and reported. A state machine operates the sequencing and control of the BIST.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eugene Atwood, Matthew B. Baecher, John F. Bulzacchelli, Stanislav Polonsky
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Publication number: 20150200792Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a separate summer circuit configured to add a respective feedback signal to a received input and a latch configured to receive an output of the summer circuit to provide different partial bit sequences based on a clock signal. A feedback circuit includes a multiplexer configured to multiplex the different partial bit sequences of each branch to assemble a full rate bit sequence and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input.Type: ApplicationFiled: March 27, 2015Publication date: July 16, 2015Inventors: John F. Bulzacchelli, Byungsub Kim
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Publication number: 20150146768Abstract: Power aware equalization in a serial communications link that includes a transmitter and a receiver, including: determining, by a power aware equalization module, a required signal eye width and a required signal eye height for signals received by the receiver; identifying one or more signal equalizers for signals transmitted over the serial communications link; identifying one or more cumulative equalizer settings that equalize signals transmitted over the serial communications link to conform with the required signal eye width and the required signal eye height for signals received by the receiver; determining power consumption values associated with each of the one or more cumulative equalizer settings; and setting the one or more signal equalizers to configuration settings in dependence upon the power consumption values associated with each of the one or more cumulative equalizer settings.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: John F. Bulzacchelli, Hayden C. Cranford, JR., Daniel M. Dreps, David W. Siljenberg
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Publication number: 20150123633Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.Type: ApplicationFiled: January 13, 2015Publication date: May 7, 2015Inventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
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Patent number: 9008169Abstract: A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.Type: GrantFiled: June 28, 2013Date of Patent: April 14, 2015Assignee: International Business MachinesInventors: John F. Bulzacchelli, Byungsub Kim
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Patent number: 8981829Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.Type: GrantFiled: August 13, 2014Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
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Publication number: 20150061744Abstract: Systems and methods are provided to regulate a supply voltage of a load circuit. For example, a system includes a voltage regulator circuit that includes a passgate device. The system includes a passgate strength calibration control module which is configured to (i) obtain information which specifies operating conditions of the voltage regulator circuit, (ii) access entries of one or more look-up tables using the obtained information, (iii) use information within the accessed entries to determine a maximum load current that could be demanded by the load circuit under the operating conditions specified by the obtained information, and to predict a passgate device width which is sufficient to supply the determined maximum load current, and (iv) set an active width of the passgate device according to the predicted passgate device width.Type: ApplicationFiled: August 13, 2014Publication date: March 5, 2015Inventors: John F. Bulzacchelli, Zeynep Toprak Deniz, Joshua D. Friedrich, Tilman Gloekler, Gregory S. Still
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Publication number: 20150054574Abstract: A system and method to regulate voltage on a chip are described. The system includes a central controller to output a digital code based on a voltage measurement from a sense point on a power grid of the chip. The system also includes a plurality of micro-regulators, each of the plurality of micro-regulators outputting a respective voltage to the power grid based on the digital code.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Applicant: International Business Machines CorporationInventors: John F. Bulzacchelli, Paul D. Muench, Michael A. Sperling, Zeynep Toprak Deniz
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Publication number: 20150054575Abstract: A system and method to regulate voltage on a chip are described. The system includes a central controller to output a digital code based on a voltage measurement from a sense point on a power grid of the chip. The system also includes a plurality of micro-regulators, each of the plurality of micro-regulators outputting a respective voltage to the power grid based on the digital code.Type: ApplicationFiled: September 30, 2014Publication date: February 26, 2015Inventors: John F. Bulzacchelli, Paul D. Muench, Michael A. Sperling, Zeynep Toprak Deniz
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Patent number: 8964825Abstract: Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.Type: GrantFiled: February 17, 2012Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Troy J. Beukema, John F. Bulzacchelli
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Patent number: 8964826Abstract: Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period.Type: GrantFiled: February 9, 2013Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Ankur Agrawal, John F. Bulzacchelli