Abstract: A constant false alarm rate video processor which uses a tapped delay line operating as a "sliding range window" to provide tap outputs corresponding to the center of the delay line and a predetermined number of discrete range cells on either side thereof. A "least of" circuit is responsive to all taps except the center tap of the delay line and the mininum signal extant on these taps is outputted and substracted (in scale factored form) from the signal of the delay line. The circuit thereby adaptively excludes target and ground clutter bias in providing the CFAR (normalized) signal output of the combination. An additional circuit arrangement is shown for digitally mapping the "least of" signal values over a predetermined threshold. The digital map output converted to analog then provides the scaled "least of" signal to be subtracted from the central range cell and for controlling the threshold of response of the mapper.