Patents by Inventor John F. Conley
John F. Conley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220213598Abstract: Microwave annealing (MWA) is used in-situ within an atomic layer deposition (ALD) chamber so that deposited material can be directly exposed to microwave heating without removing the material from the ALD chamber. A microwave source is integrated in-situ within an ALD chamber to provide direct microwave interaction with defects and impurities in layer(s) deposited on a substrate. As such, the need to remove the substrate and film between cycles for annealing is eliminated. In-situ MWAs allow for improved ALD film properties at lower temperature, without negatively impacting throughput.Type: ApplicationFiled: May 19, 2020Publication date: July 7, 2022Applicant: Oregon State UniversityInventor: John F. Conley, Jr.
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Publication number: 20190114602Abstract: A system of providing a receiver of payments access to a plurality of payment sources, is described that includes a configuration tool listing a plurality of payment sources available to the receiver of payments and configured to allow the receiver to select one or more disparate payment sources from which it will accept payments. The system then provides a payment interface for the receiver of payments displayable to customers of the receiver. A payment transaction database stores data related to financial transactions carried out on behalf of the receiver of payments. The system also includes a payment hub that provides an interface between the receiver of payments and the selected payment sources.Type: ApplicationFiled: October 16, 2018Publication date: April 18, 2019Applicant: ModoPayments, LLCInventors: Cevat Kerim Incedayi, Adam D. Schnaare, Bruce Parker, Gregory W. Harvey, John F. Conley, III, Colm Bergin
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Patent number: 8053266Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.Type: GrantFiled: April 13, 2010Date of Patent: November 8, 2011Assignee: Sharp Laboratories of America, Inc.Inventors: Changqing Zhan, Paul J. Schuele, John F. Conley, Jr., John W. Hartzell
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Publication number: 20100197065Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-Site, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Inventors: Changqing Zhan, Paul J. Schuele, John F. Conley, JR., John W. Hartzell
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Patent number: 7763947Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.Type: GrantFiled: March 13, 2007Date of Patent: July 27, 2010Assignee: Sharp Laboratories of America, Inc.Inventors: Changqing Zhan, Paul J. Schuele, John F. Conley, Jr., John W. Hartzell
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Patent number: 7597757Abstract: A ZnO film with a C-axis preference is provided with a corresponding fabrication method. The method includes: forming a substrate; forming an amorphous Al2O3 film overlying the substrate; and, forming a ZnO film overlying the Al2O3 film at a substrate temperature of about 170° C., having a C-axis preference responsive to the adjacent Al2O3 film. The substrate can be a material such as Silicon (Si) (100), Si (111), Si (110), quartz, glass, plastic, or zirconia. The Al2O3 film can be deposited using a chemical vapor deposition (CVD), atomic layer deposition (ALD), or sputtering process. Typically, the Al2O3 layer has a thickness in the range of about 3 to 15 nanometers (nm). The step of forming the ZnO film having a C-axis preference typically means that the ZnO film has a (002) peak at least 5 times greater than the (100) peak, as measured by X-ray diffraction (XRD).Type: GrantFiled: November 17, 2005Date of Patent: October 6, 2009Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono
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Patent number: 7589464Abstract: A device and a fabrication method are provided for an EL device with a nanotip-contoured phosphor layer. The method comprises: forming a bottom electrode with nanotips; forming a phosphor layer overlying the bottom electrode, having irregularly-shaped top and bottom surfaces; and, forming a top electrode overlying the phosphor layer. The bottom electrode top surface has a nanotip contour, and the phosphor layer irregularly-shaped top and bottom surfaces have contours approximately matching the bottom electrode top surface nanotip contour. In one aspect, a contoured bottom dielectric is interposed between the bottom electrode and the phosphor layer, having top and bottoms surfaces with contours approximately matching the nanotip contour. Likewise, a top dielectric may be interposed between the top electrode and the phosphor layer, having a bottom surface with a contour approximately matching the contour of phosphor layer top surface.Type: GrantFiled: March 1, 2005Date of Patent: September 15, 2009Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., David R. Evans, Wei Gao, Yoshi Ono
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Patent number: 7528695Abstract: A method of selectively enhancing the sensitivity of a metal oxide sensor includes fabricating a ZnO sensor having a ZnO sensor element therein; and exposing the ZnO sensor element to a plasma stream.Type: GrantFiled: February 23, 2006Date of Patent: May 5, 2009Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono
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Patent number: 7473640Abstract: A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.Type: GrantFiled: February 23, 2004Date of Patent: January 6, 2009Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Wei Gao
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Patent number: 7462499Abstract: A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).Type: GrantFiled: October 28, 2005Date of Patent: December 9, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Lisa H. Stecker, Sheng Teng Hsu, Josh M. Green, Lifeng Dong, Jun Jiao
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Patent number: 7442415Abstract: A method of forming a layer of high-k dielectric material in an integrated circuit includes preparing a silicon substrate; forming a high-k dielectric layer by a sequence of ALD cycles including: depositing a first layer of metal ligand using ALD with an oxygen-containing first precursor; and depositing a second layer of metal ligand using ALD with a second precursor; repeating the sequence of ALD cycles N times until a near-critical thickness of metal oxide is formed; annealing the substrate and metal oxide layers every N ALD cycles in an elevated temperature anneal; repeating the sequence of ALD cycles and elevated temperature anneals until a high-k dielectric layer of desired thickness is formed; annealing the substrate and the metal oxide layers in a final annealing step; and completing the integrated circuit.Type: GrantFiled: April 11, 2003Date of Patent: October 28, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Gregory M. Stecker
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Patent number: 7309621Abstract: A method of fabricating a nanowire CHEMFET sensor mechanism includes preparing a silicon substrate; depositing a polycrystalline ZnO seed layer on the silicon substrate; patterning and etching the polycrystalline ZnO seed layer; depositing an insulating layer over the polycrystalline ZnO seed layer and the silicon substrate; patterning and etching the insulating layer to form contact holes to a source region and a drain region; metallizing the contact holes to form contacts for the source region and the drain region; depositing a passivation dielectric layer over the insulating layer and the contacts; patterning the passivation layer and etching to expose the polycrystalline ZnO seed layer between the source region and the drain region; and growing ZnO nanostructures on the exposed ZnO seed layer to form a ZnO nanostructure CHEMFET sensor device.Type: GrantFiled: April 26, 2005Date of Patent: December 18, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Lisa H. Stecker
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Patent number: 7303631Abstract: Patterned zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. The seed layer is patterned, such as by etching, and growth of at least one zinc-oxide nanostructure is induced substantially over the patterned seed layer by, for example, exposing the patterned seed layer to zinc vapor in the presence of a trace amount of oxygen. The seed layer can alternatively be formed by using a spin-on technique, such as a metal organic deposition technique, a spray pyrolisis technique, an RF sputtering technique or by oxidation of a zinc thin film layer formed on the substrate.Type: GrantFiled: October 29, 2004Date of Patent: December 4, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Lisa H. Stecker
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Patent number: 7208768Abstract: A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II–VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.Type: GrantFiled: April 30, 2004Date of Patent: April 24, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Yoshi Ono, Wei Gao, John F. Conley, Jr., Osamu Nishio, Keizo Sakiyama
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Patent number: 7199029Abstract: Zinc-oxide nanostructures are formed by forming a pattern on a surface of a substrate. A catalyst metal, such as nickel, is formed on the surface of the substrate. Growth of at least one zinc oxide nanostructure is induced on the catalyst metal substantially over the pattern on the surface of the substrate based on a vapor-liquid-solid technique. In one exemplary embodiment, inducing the growth of at least one zinc-oxide nanostructure induces growth of each zinc-oxide nanostructure substantially over a patterned polysilicon layer. In another exemplary embodiment, when growth of at least one zinc-oxide nanostructure is induced, each zinc-oxide nanostructure grows substantially over an etched silicon substrate layer.Type: GrantFiled: October 1, 2004Date of Patent: April 3, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Lisa H. Stecker, Gregory M. Stecker
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Patent number: 7192802Abstract: Zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. Growth of at least one zinc-oxide nanostructure is induced on the seed layer. The seed layer can alternatively be formed by using a spin-on technique, such as a metal organic deposition technique, a spray pyrolisis technique, an RF sputtering technique or by oxidation of the seed layer.Type: GrantFiled: October 29, 2004Date of Patent: March 20, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Lisa H. Stecker, John F. Conley, Jr.
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Patent number: 7160819Abstract: A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and deionized water; depositing a layer of ZnO on the wafer by ALD using diethyl zinc and H2O at a temperature of between about 140° C. to 170° C.; and removing the blocking agent from the wafer.Type: GrantFiled: April 25, 2005Date of Patent: January 9, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, David R. Evans
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Patent number: 7053009Abstract: An atomic layer deposition method to deposit an oxide nanolaminate thin film is provided. The method employs a nitrate ligand in a first precursor as an oxidizer for a second precursor to form the oxide nanolaminates. Using a hafnium nitrate precursor and an aluminum precursor, the method is well suited for the deposition of a high k hafnium oxide/aluminum oxide nanolaminate dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.Type: GrantFiled: March 24, 2005Date of Patent: May 30, 2006Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Rajendra Solanki
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Patent number: 7029944Abstract: A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array.Type: GrantFiled: September 30, 2004Date of Patent: April 18, 2006Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Wei Gao, David R. Evans
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Patent number: 6930059Abstract: An atomic layer deposition method to deposit an oxide nanolaminate thin film is provided. The method employs a nitrate ligand in a first precursor as an oxidizer for a second precursor to form the oxide nanolaminates. Using a hafnium nitrate precursor and an aluminum precursor, the method is well suited for the deposition of a high k hafnium oxide/aluminum oxide nanolaminate dielectric for gate dielectric or capacitor dielectric applications on a hydrogen-terminated silicon surface.Type: GrantFiled: February 27, 2003Date of Patent: August 16, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Yoshi Ono, Rajendra Solanki