Abstract: A semiconductor memory test system with improved fault data processing and display capabilities. The memory tester includes a lossless data compressor for failure data. Compression allows failure data to be more rapidly transferred to a display device that is part of a work station controlling the memory tester. It also reduces the amount of data that must be stored in the display memory, thereby providing a cost effective way to store data from multiple tests. By allowing data for multiple tests to be stored, the data from a prior test can be used to control the formatting of data for a subsequent test. Such formatting is useful for such things as observing failure mechanisms as the operating temperature or speed of the semiconductor memory under test increases.

Abstract: A semiconductor tester with features to facilitate testing of embedded memories. The circuitry allows tests to be generated algorithmically, but can be used in conjunction with scan test structures of semiconductor devices. Programming and debug time can be significantly reduced. The tester includes an algorithmic pattern generator that can generate a pattern for testing a memory. The tester also includes serializer circuits coupled to the algorithmic pattern generators that can convert the test pattern generated by the algorithmic pattern generator into one or more serial bit streams useful for scan testing an embedded memory.