Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.

Abstract: Method and apparatus to calibrate sampling phases of a multi-phase sampling system. The method includes on-chip generating a pristine phase reference pattern signal for use in generating at least one reference output signal from a data path; sampling, responsive to a clock signal, the at least one reference output signal to obtain samples; and modifying a phase of the clock signal to align the obtained samples to pattern edges of at least one reference output signal. Both symmetric and asymmetric duty cycle distortion are removed from the pristine phase reference pattern signal input to the data path. The effects of asymmetric distortion in the data path output signal upon the phase calibration are cancelled by periodically inverting the at least one reference output signal.

Abstract: Methods and deserializer circuits are provided for generating a parallel data signal by converting serial data of a serial data signal to parallel data. In a particular embodiment, the deserializer circuit includes a logic divider configured to generate based on a half rate clock, a quarter rate clock, a mode rate clock, and a selection control signal. The deserializer circuit includes a first set of latches for sampling and aligning the serial data from the serial data signal into the deserializer circuit based on the half rate clock. The deserializer circuit also includes a shift register including a second set of latches configured to latch the output of the first set of latches based on the quarter rate clock generated by the logic divider. In the particular embodiment, the deserializer circuit also includes multiplexer logic configured to output the parallel data signal including latching data from the shift register.

Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.

Abstract: Apparatuses for generating negative impedance compensation are provided. Embodiments include a differential amplifier having a first output and a second output; a capacitor coupled between the first output and the second output of the differential amplifier; a first negative impedance cross-coupled circuit having a first output and a second output; and a resistance control circuit coupled in series between the first output and the second output of the differential amplifier and the first output and the second output of the first negative impedance cross-coupled circuit.

Abstract: An analog error amplifier includes an amplifier circuit and a replica bias circuit that together produce an output signal representing a difference between an input signal and a reference signal. The amplifier circuit produces the output signal in response to the input signal and a bias signal provided by the replica bias circuit. The bias signal may establish a reference threshold of a basic amplifier in the amplifier circuit. The replica bias circuit produces the bias signal in response to the reference signal and drives the bias signal to be equal to the reference signal. The replica bias circuit may include a plurality of amplifier stages. The bias signal produced by a single replica bias circuit may be provided to a plurality of amplifier circuits to provide a plurality of error amplifiers for a single reference signal.

Abstract: Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.

Abstract: Method and apparatus for testing a parallel optical transceiver are provided. One embodiment provides a built-in self-testing (BIST) parallel optical transceiver comprising a full-rate clock test pattern generator and a clock divider circuit connected to provide a half-rate clock signal to one of the one or more transmitter channels, and an error detector comprising one or more error detection circuits connected to one or more receiver channels and configured to receive the half-rate clock signal. Another embodiment provides a method for testing a parallel optical transceiver, comprising: generating a full-rate clock test pattern to one or more transmitter channels; providing a half-rate clock signal to one of the one or more transmitter channels utilizing a clock divider circuit; transmitting test pattern and half-rate clock signals to one or more corresponding receiver channels; and detecting error utilizing one or more error detection circuits connected to receive the half-rate clock signal.

Abstract: A method of designing a high Q inductor for implementation in multiple metalization levels in conventional integrated circuit technology uses a software assisted iterative technique to achieve a design Q factor. The inductor turns utilize the multiple metalization levels to reduce inductor resistance.

Abstract: A novel bias generator circuit for a voltage controlled oscillator is described. The bias generator allows the VCO frequency to be made essentially independent of the supply voltage and temperature.

Abstract: The present invention is a translator circuit which receives an input compatible with a differential current switch type of circuit and transmits an output compatible with a super buffer logic type of circuit. The translator circuit has a gain stage interposed between an input and output stage which both level shift the signal downward. The gain stage provides the translator circuit with the performance necessary to avoid attenuation of the signal between receiving the input signal and transmitting the output signal. The input and output stages buffer the gain stage by shifting the voltage level of the translator downward in two stages. The translator circuit provides its own voltage reference circuits which are compatible with the power supply of the DCS and SBL circuits. The reference circuits are self compensating for temperature effects. The translator circuit of the present invention allows different types of circuit families to be inexpensively designed on the same integrated circuit chip.

Abstract: A clock recovery circuit and demultiplexer circuit which operate at half the data rate of a received data stream. The half-speed clock recovery circuit generates a 0 and 90-degree clock at half the rate of the incoming data. These clocks are sampled by a pair of edge triggered flip-flops using the transitions of the received data as triggers. The outputs of these flip-flops are exclusive OR-ed to provide a signal indicating whether the generated clock leads or lags the received data. The half-speed 1:2 demultiplexer circuit uses the rising and falling edges of a half-speed 90-degree clock to latch the received data through a pair of flip-flops. The outputs of these flip-flops, each triggered by a different edge of the clock, make up two demultiplexed data streams. The clock recovery and demultiplexer circuits of the present invention can be extended to operate at lower clock rates and configured to provide wider demultiplexing.

Abstract: A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.

Abstract: A GaAs differential current switch (DCS) logic family is disclosed. Two cross-coupled, push-pull output buffer stages are coupled to the DCS logic circuit to increase the gain and to improve noise margins. The circuit is compatible with other GaAs logic families such as super buffer logic (SBL) or source follower logic (SFFL).

Abstract: A voltage controlled oscillator is formed of a plurality of cascaded inverter stages in a ring configuration. Each inverter stage is a grounded emitter circuit having an active pull-up stage in order to achieve a short stage delay. The frequency of the ring oscillator is determined by the number of inverter stages, and the gain is selectable by coupling an external control voltage to only certain of the inverters. The VCO may be fabricated on a single integrated circuit along with the other circuits necessary to form a phase locked loop or other frequency generation system.