Patents by Inventor John F. Phinney

John F. Phinney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160012535
    Abstract: A system for deriving and managing RIA knowledge employs a data collection server and data processing system. The data collection server is configured to communicate with at least one data source to collect publically-available information pertaining to RIAs and stores such information in a first database. The data processing system processes the publically-available information stored in the first database to derive artifacts representing the publically-available information as well as additional artifacts that represent useful information beyond the publically-available information, and stores the artifacts and additional artifacts in a second database for output and/or analysis by users. The artifacts and additional artifacts that pertain to a particular RIA can be derived from both structured and unstructured data reported by the particular RIA to a regulatory authority.
    Type: Application
    Filed: June 29, 2015
    Publication date: January 14, 2016
    Applicant: CONVERGENCE, INC.
    Inventors: John F. Phinney, JR., George F. Evans, Russell Klein, Rodney Lopez, Curtis J. Kjellman, Matthew C. Smith, Gaurav Patil
  • Patent number: 7934032
    Abstract: Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: April 26, 2011
    Assignee: EMC Corporation
    Inventors: Steven D. Sardella, Stephen Strickland, James C. Tryhubczak, John F. Phinney