Patents by Inventor John FAISTL

John FAISTL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for supporting speculative memory optimizations
    Patent number: 10853078
    Abstract: A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 1, 2020
    Assignee: INTEL CORPORATION
    Inventors: Vineeth Mekkat, Mark Dechene, Zhongying Zhang, John Faistl, Janghaeng Lee, Hou-Jen Ko, Sebastian Winkel, Oleg Margulis
  • HARDWARE PROFILER TO TRACK INSTRUCTION SEQUENCE INFORMATION INCLUDING A BLACKLISTING MECHANISM AND A WHITELISTING MECHANISM
    Publication number: 20200210193
    Abstract: A processor includes a set of execution units in an out-of-order execution pipeline, and a hardware profiler in the out-of-order execution pipeline coupled to the set of execution units and to profile instructions executed by the set of execution units, the hardware profiler to generate a profiling interrupt, the profiling interrupt to initiate an optimization of a basic block of instructions in response to determining that a whitelist bit is set corresponding to the basic block of instructions, the whitelist bit to identify the basic block of instructions for immediate optimization.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Inventors: Sangeeta BHATTACHARYA, Mark DECHENE, John FAISTL, Jason M. AGRON, Sebastian WINKEL, Rangeen BASU ROY CHOWDHURY
  • METHOD AND APPARATUS FOR SUPPORTING SPECULATIVE MEMORY OPTIMIZATIONS
    Publication number: 20200201645
    Abstract: A processor includes a store buffer to store store instructions to be processed to store data in main memory, a load buffer to store load instructions to be processed to load data from main memory, and a loop invariant code motion (LICM) protection structure coupled to the store buffer and the load buffer. The LPT tracks information to compare an address of a store or snoop microoperation with entries in the LICM and re-loads a load microoperation of a matching entry.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Vineeth MEKKAT, Mark DECHENE, Zhongying ZHANG, John FAISTL, Janghaeng LEE, Hou-Jen KO, Sebastian WINKEL, Oleg MARGULIS