Abstract: Described herein is a graphics processor configured to perform time based frame predication to bypass execution of a command buffer based on a comparison with time stamps stored in a time stamp buffer that tracks execution time for command buffers. The graphics processors can bypass a frame that will not complete in time for a target display update and trigger neural frame generation to generate the frame data for the bypassed command buffer. Dynamic render scaling is also described.

Abstract: Described herein is a technique to enhance the responsiveness of gameplay for a 3D gaming application while maintaining the ability to enqueue multiple frames for processing on the GPU. Each frame or a set of workloads within a frame is submitted to the GPU with predication, such that the indicated rendering and resource manipulation commands are not actually performed if the predication condition is enabled. A low latency command can be submitted to the GPU via a copy engine command queue. The command will cause the copy engine to enable or disable predication for command buffers in the command queue. When predication for queued command buffers is enabled, command buffers for workloads that are not related to the workload that is generated in response to the user input are bypassed. High priority command buffers that include workloads generated in response to user input can then be executed immediately.

Abstract: Methods, systems and apparatuses may provide for technology that marks a graphics resource as a flush candidate during a current frame, conducts an early flush of a command buffer from the graphics resource if a write event is detected with respect to the graphics resource during a subsequent frame, and bypasses the early flush if the write event is not detected with respect to the graphics resource during the subsequent frame. In one example, the graphics resource is marked as the flush candidate in response to a read back operation of the host processor with respect to the graphics resource, wherein the read back operation retrieves a query result and/or maps a staging resource.

Abstract: An apparatus and method for scheduling threads on local and remote processing resources.

Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.

Abstract: Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.

Abstract: An apparatus and method for scheduling threads on local and remote processing resources.

Abstract: An apparatus and method for scheduling threads on local and remote processing resources.

Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.

Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.

Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.

Abstract: An apparatus and method for scheduling threads on local and remote processing resources.

Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.

Abstract: Apparatus and method for a multi-frequency vertex shader. For example, one embodiment of a graphics processing apparatus comprises a plurality of vertex caches to store vertex data associated with graphics primitives; and graphics execution circuitry to execute vertex shaders operable at different processing rates for different sets of the vertex data, each of the different sets of vertex data to having a different type of identifier associated therewith to identify the vertex data.

Abstract: An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.