Abstract: An adapter block assembly includes an adapter block, a circuit board arrangement, and a cover attached to the adapter block so that the circuit board arrangement is held to the adapter block by the cover. Contact assemblies can be disposed between the adapter block and the circuit board arrangement. The cover can be latched, heat staked, or otherwise secured to the adapter block. Each component of the adapter block assembly can include one or more parts (e.g., multiple adapter blocks, multiple circuit boards, and/or multiple cover pieces).

Abstract: Certain aspects of the present disclosure provide techniques for operating a wireless device pursuant to radio frequency (RF) exposure compliance. A method that may be performed by a wireless device includes switching sensing circuitry to a first mode in response to one or more first criteria being satisfied; switching the sensing circuitry to a second mode in response to one or more second criteria being satisfied; and transmitting a signal at a transmit power determined based at least in part on a radio frequency (RF) exposure limit, and if the sensing circuitry is operating in the second mode, on one or more measurements associated with the sensing circuitry.

Abstract: A hygienic filter and disposal apparatus comprising a main compartment a base platform, a front end, and a back end, and adapted to contain granular material and waste; a secondary compartment adapted to contain granular material; a door connecting the main compartment to the secondary compartment; and a filter element, comprising porous walls around a cavity and a first opening into said cavity, the walls adapted to filter waste out of the granular material; wherein the back end is proximate to the first opening at a first position where the front end and the back end of the base platform are level; wherein in a second position the front end is lifted higher than the back end and the granular material and waste are directed through the first opening into the cavity; wherein in the second position the filter element retains waste in the cavity and permits the granular material to fall through the porous walls into the secondary compartment; wherein in a third position the back end is higher than the front end

Abstract: A hygienic filter and disposal apparatus comprising a main compartment a base platform, a front end, and a back end, and adapted to contain granular material and waste; a secondary compartment adapted to contain granular material; a door connecting the main compartment to the secondary compartment; and a filter element, comprising porous walls around a cavity and a first opening into said cavity, the walls adapted to filter waste out of the granular material; wherein the back end is proximate to the first opening at a first position where the front end and the back end of the base platform are level; wherein in a second position the front end is lifted higher than the back end and the granular material and waste are directed through the first opening into the cavity; wherein in the second position the filter element retains waste in the cavity and permits the granular material to fall through the porous walls into the secondary compartment; wherein in a third position the back end is higher than the front end

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: An optical device includes a substrate having a surface, a peripheral edge, an area of vision, and a boundary portion of the surface between the peripheral edge and the area of vision. At least a portion of the boundary portion is textured. A coating is applied to the surface of the substrate over the area of vision and the textured boundary portion. In some embodiments, the substrate is comprised of a polymeric material and the coating is comprised of multiple layers of dielectric material and the substrate is textured such that the textured portion increases adhesion and the durability of the dielectric coating.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: Techniques are disclosed relating to cache coherency and snoop filtering. In some embodiments, an apparatus includes multiple processor cores and corresponding filter circuitry that is configured to filter snoops to the processor cores. The filter circuitry may implement a Bloom filter. The filter circuitry may include a first set of counters. The filter circuitry may determine a group of counters in the first set based on applying multiple hash functions to an incoming address. For allocations, the filter circuitry may increment the counters in the corresponding group of counters; for evictions, the filter circuitry may decrement the counters in the corresponding group of counters; and for snoops, the filter circuitry may determine whether to filter the snoop based on whether any of the counters in the corresponding group are at a start value.

Abstract: Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple processors and a memory connect interface may be configured to provide an interface for the processors to the shared memory. The memory connect interface may include an arbiter for atomic memory operations from the processors. In response to an atomic memory operation, the arbiter may perform an atomic memory operation procedure including setting a busy flag for an address of the atomic memory operation, blocking subsequent memory operations from any of the processors to the address while the busy flag is set, issuing the atomic memory operation to the shared memory, and in response to an acknowledgement of the atomic memory operation from the shared memory, clearing the busy flag and allowing subsequent memory operations from the processors for the address to proceed to the shared memory.

Abstract: A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.

Abstract: A method and apparatus for memory paging is disclosed. A system includes a plurality of processor cores each configured to initiate requests to a memory by providing a physical address without a virtual address. A first cache subsystem is shared by each of a first subset of the plurality of processor cores. Responsive to receiving a memory access request from a processor core of the first subset, the first cache subsystem determines if a physical address of the request is in a first paged region of memory with respect to the first subset. If the physical address is in the paged region, the cache subsystem is configured to access a set of page attributes for a page corresponding to the physical address from a page attribute table responsive that is shared by each of the first subset of the plurality of processor cores.

Abstract: An optical device includes a substrate having a surface, a peripheral edge, an area of vision, and a boundary portion of the surface between the peripheral edge and the area of vision. At least a portion of the boundary portion is textured. A coating is applied to the surface of the substrate over the area of vision and the textured boundary portion. In some embodiments, the substrate is comprised of a polymeric material and the coating is comprised of multiple layers of dielectric material and the substrate is textured such that the textured portion increases adhesion and the durability of the dielectric coating.

Abstract: An endoscopic tissue anchor deployment device includes a handle, an elongated shaft defining an internal lumen, and an end effector attached to the distal end of the elongated shaft. A tissue anchor catheter is removably inserted through the lumen of the elongated shaft, the catheter having a tissue anchor assembly that is deployable from its distal end. In some embodiments, the handle includes a pin and track assembly that define a series of handle actuation steps corresponding to deployment steps for the deployment device end effector and the tissue anchor catheter. In some embodiments, the handle includes a catheter stop member that prevents movement of the tissue anchor catheter under certain circumstances, and a handle stop member that prevents actuation of the handle under certain circumstances.

Abstract: A laser eye protection (LEP) system for a helmet having a helmet-mounted display (HMD) system. The LEP system includes a large outer visor, which provides ballistic protection, LEP and a display surface for the HMD, and a smaller inner visor, which also provides LEP. LEP is split between the two visors, so that the outer visor can block light in a wavelength that overlaps with the peak wavelength range of the HMD without impairing the wearer's ability to view HMD imagery. The outer visor also preferably does not block near IR light, which allows image-enhancement devices to be positioned within the protective envelope of the outer visor while the smaller inner visor protects the wearer from near IR threats.

Abstract: A laser eye protection (LEP) system for a helmet having a helmet-mounted display (HMD) system. The LEP system includes a large outer visor, which provides ballistic protection, LEP and a display surface for the HMD, and a smaller inner visor, which also provides LEP. LEP is split between the two visors, so that the outer visor can block light in a wavelength that overlaps with the peak wavelength range of the HMD without impairing the wearer's ability to view HMD imagery. The outer visor also preferably does not block near IR light, which allows image-enhancement devices to be positioned within the protective envelope of the outer visor while the smaller inner visor protects the wearer from near IR threats.

Abstract: An endoscopic tissue anchor deployment device includes a handle, an elongated shaft defining an internal lumen, and an end effector attached to the distal end of the elongated shaft. A tissue anchor catheter is removably inserted through the lumen of the elongated shaft, the catheter having a tissue anchor assembly that is deployable from its distal end. In some embodiments, the handle includes a pin and track assembly that define a series of handle actuation steps corresponding to deployment steps for the deployment device end effector and the tissue anchor catheter. In some embodiments, the handle includes a catheter stop member that prevents movement of the tissue anchor catheter under certain circumstances, and a handle stop member that prevents actuation of the handle under certain circumstances.

Abstract: A memory addressing technique using load buffers is described. More particularly, embodiments of the invention relate to a method and apparatus for accessing data in a computer system by exploiting addressing mode information within an instruction such that if present, data may be obtained from the load buffers, rather than accessing a cache memory or other memory device within the computer system.

Abstract: A memory addressing technique using load buffers to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.

Abstract: Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the first latch, and a scan path to connect the output of the second latch to an input of a second save/restore cell of the save/restore chain. The apparatus is useful for fast context switching.