Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: A composite roofing element comprises a first layer of aggregate based material, a second layer of material having a density less than that of the first layer and has a wedge shaped region depending from its underside. The wedge shaped region is preferably integral with the second layer which can be made of an expanded polymer, expanded polystyrene being particularly suitable. Overlapping structure on the side edges and a recess in the thick end of the wedge enable adjacent elements to interlock with each other. By using such lightweight roofing elements the requirement for a substantial load bearing supporting structure is reduced.

Abstract: Roofing elements, particularly suitable for use on flat roof constructions, are provided with co-operating means on each of at least one pair of opposite side edges for co-operation with at least two adjacent elements on each of the side edges. When assembled, movement of any one element involves movement of at least one co-operating element on each of the opposite sides edges. Such bidirectional co-operation results in an interlocked roof construction wherein the uplifting of individual roofing elements by the action of the wind or other forces is substantially eliminated. Uplift pressure caused by wind passing over the roof surface can be further reduced by providing communicating air-flow passages between co-operating elements.

Abstract: An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line is used to signal the ECC when data from the DRAM arrays is valid during a fetch operation; the same dummy data line also signals the DRAM arrays when the data from the ECC is valid during a write-back operation.

Abstract: A lightweight concrete product in the form of a concrete roof tile is made from a cementitious mixture comprising a porous lightweight aggregate, an hydraulic cement, water, an agent for enhancing, flexural strength and an agent for enhancing the water retention capacity of the lightweight aggregate, the proportions being such that the product has satisfactory impact and flexural strengths.

Abstract: A logic system including a first logic block for providing first differential outputs; a second logic block, identical to the first logic block, for providing second differential outputs; a fault detecting device, coupled to the first logic block, for detecting a fault in the first differential outputs; and a selecting device, coupled to the first and second logic blocks and to the fault detecting device, for selecting an output of one of the first and second logic blocks depending on whether the fault detecting device detects a fault.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: An interlocking roof tile which can be made by extrusion, pressing or moulding has an upper edge; a lower edge which is visible in use when the tile is laid in overlapping relationship with at least one tile of a next adjacent line of the tiles; an upper surface; a lower surface; a supporting understructure; two oppositely facing side edges; an underlock extending along one of the side edges and an overlock extending along the other of the side edges, the underlock having a lower end and an under surface which forms part of the under surface of the tile, and a lower edge portion having an under surface which includes a part of the under surface of the underlock, and which overlaps, in use, at least one tile of the next adjacent line of the tiles, characterized in that the upper surface of the tile extends continuously from the lower edge to the upper edge, in that the upper and lower surfaces are cambered from the lower edge to the upper edge and are substantially flat when considered in cross-section taken a

Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW.

Abstract: An interlocking roof tile (1) of which the leading end portion (12) at least as far as the lower end of, and including the underlock (6) is tapered in the direction of the leading edge (5) of the tile (1).

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.

Abstract: A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available each of a plurality of sub-arrays of normal memory.

Abstract: This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

Abstract: A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line.