Patents by Inventor John Frank Surowka

John Frank Surowka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for reducing coefficient of thermal expansion in chip attach packages
    Patent number: 6841026
    Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. One embodiment of the reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: January 11, 2005
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Robert Blumberg, Robert Maynard Japp, William John Rudik, John Frank Surowka
  • Method for reducing coefficient of thermal expansion in chip attach packages
    Patent number: 6586352
    Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structure comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Robert Blumberg, Robert Maynard Japp, William John Rudik, John Frank Surowka
  • Method for reducing coefficient of thermal expansion in chip attach packages
    Publication number: 20030000081
    Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. One embodiment of the reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat.
    Type: Application
    Filed: March 26, 2002
    Publication date: January 2, 2003
    Applicant: International Business Machines Corporation
    Inventors: Lawrence Robert Blumberg, Robert Maynard Japp, William John Rudik, John Frank Surowka
  • Method for reducing coefficient of thermal expansion in chip attach packages
    Patent number: 6387830
    Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.
    Type: Grant
    Filed: March 10, 1999
    Date of Patent: May 14, 2002
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Robert Blumberg, Robert Maynard Japp, William John Rudik, John Frank Surowka
  • Laminated electroplating rack and connection system for optimized plating
    Patent number: 6176985
    Abstract: An electroplating apparatus provides high current electrical connections in a small area to a workpiece. The contact area may use a dendrite surface to improve the connection. An insulative gasket prevents electroplating fluids from entering the region about the contact area. A heavy core laminated within a supporting structure provides uniform current distribution of high electrical currents to the dendrite covered contact areas.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: January 23, 2001
    Assignee: International Business Machines Corporation
    Inventors: Francis J. Downes, Jr., Raymond Thomas Galasco, Robert Maynard Japp, John Frank Surowka
  • Method for reducing coefficient of thermal expansion in chip attach packages
    Patent number: 6136733
    Abstract: A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Robert Blumberg, Robert Maynard Japp, William John Rudik, John Frank Surowka