Patents by Inventor JOHN FREDIANI
JOHN FREDIANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11041907Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.Type: GrantFiled: October 2, 2019Date of Patent: June 22, 2021Assignee: ADVANTEST CORPORATIONInventors: Ben Rogel-Favila, Mei-Mei Su, John Frediani, Shunji Tachibana
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Patent number: 10634723Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.Type: GrantFiled: January 3, 2018Date of Patent: April 28, 2020Assignee: ADVANTEST CORPORATIONInventors: Ben Rogel-Favila, Mei-Mei Su, John Frediani, Shunji Tachibana
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Publication number: 20200033408Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT,a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.Type: ApplicationFiled: October 2, 2019Publication date: January 30, 2020Inventors: Ben ROGEL-FAVILA, Mei-Mei SU, John FREDIANI, Shunji TACHIBANA
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Patent number: 10161993Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data and a comparator circuit configured to compare data.Type: GrantFiled: February 21, 2013Date of Patent: December 25, 2018Assignee: Advantest CorporationInventors: John Frediani, Andrew Niemic
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Publication number: 20180188322Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system comprises: a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by said controller processor, said plurality of programmable accelerator circuits for providing input test signals and for capturing output test signals; and a plurality of load boards respectively coupled to said plurality of programmable accelerator circuits, said plurality of load boards for applying said input test signals to a plurality of devices under test (DUTs) and for capturing said output test signals therefrom. In one exemplary implementation, each of said plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from said respective DUT; and sideband connectors. The sideband connectors receive test related information from said DUT.Type: ApplicationFiled: January 3, 2018Publication date: July 5, 2018Inventors: Ben ROGEL-FAVILA, Mei-Mei SU, John FREDIANI, Shunji TACHIBANA
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Patent number: 9810729Abstract: A method for testing using an automated test equipment is presented. The method comprises transmitting instructions for performing an automated test from a system controller to a tester processor, wherein the instructions comprise parameters for a descriptor module. The method also comprises programming a reconfigurable circuit for implementing the descriptor module onto an instantiated FPGA block coupled to the tester processor. Further, the method comprises interpreting the parameters from the descriptor module using the reconfigurable circuit, wherein the parameters control execution of a plurality of test operations on a DUT coupled to the instantiated FPGA block. Additionally, the method comprises constructing at least one packet in accordance with the parameters, wherein each one of the at least one packet comprises a command for executing a test operation on the DUT. Finally, the method comprises performing a handshake with the DUT to route the at least one packet to the DUT.Type: GrantFiled: February 28, 2013Date of Patent: November 7, 2017Assignee: ADVANTEST CORPORATIONInventor: John Frediani
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Publication number: 20140236524Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: ADVANTEST CORPORATIONInventors: John FREDIANI, Andrew Niemic
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Publication number: 20140236526Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment comprises a system controller for controlling a test program, wherein the system controller is coupled to a bus. The tester system further comprises a plurality of modules also coupled to the bus, where each module is operable to test a plurality of DUTs. Each of the modules comprises a tester processor coupled to the bus and a plurality of configurable blocks communicatively coupled to the tester processor. Each of the configurable blocks is operable to communicate with an associated DUT and further operable to be programmed with a communication protocol for communicating test data to and from said associated device under test.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: ADVANTEST CORPORATIONInventors: JOHN FREDIANI, ANDREW NIEMIC
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Publication number: 20090132870Abstract: A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.Type: ApplicationFiled: November 15, 2007Publication date: May 21, 2009Applicant: INOVYS CORPORATIONInventors: PHILLIP BURLISON, MEI-MEI SU, JOHN FREDIANI
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Publication number: 20080209288Abstract: An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Applicant: INOVYS CORPORATIONInventors: PHIL BURLISON, JOHN FREDIANI