Patents by Inventor John G. Gaudiello
John G. Gaudiello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11244869Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: GrantFiled: April 28, 2020Date of Patent: February 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Patent number: 10943902Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.Type: GrantFiled: August 13, 2019Date of Patent: March 9, 2021Assignee: International Business Machines CorporationInventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
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Patent number: 10756088Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.Type: GrantFiled: August 15, 2019Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
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Publication number: 20200258790Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Patent number: 10685886Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: GrantFiled: December 15, 2017Date of Patent: June 16, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Patent number: 10593672Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.Type: GrantFiled: January 8, 2018Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
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Publication number: 20190371797Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.Type: ApplicationFiled: August 15, 2019Publication date: December 5, 2019Inventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
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Publication number: 20190363082Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.Type: ApplicationFiled: August 13, 2019Publication date: November 28, 2019Inventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
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Publication number: 20190214386Abstract: A method for manufacturing a semiconductor device includes growing a first strained semiconductor layer on a substrate, the first strained semiconductor layer having a first type of strain, wherein the substrate comprises a first crystalline orientation at a top surface of the substrate, forming at least one trench in the substrate, wherein exposed sidewalls of the at least one trench have a second crystalline orientation different from the first crystalline orientation, growing a buffer layer in the at least one trench from the exposed sidewalls of the trench, and growing a second strained semiconductor layer on the buffer layer, the second strained semiconductor layer having a second type of strain, wherein the first type of strain is different from the second type of strain.Type: ApplicationFiled: January 8, 2018Publication date: July 11, 2019Inventors: Juntao Li, Kangguo Cheng, John G. Gaudiello
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Publication number: 20190189521Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Inventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
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Patent number: 10170548Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.Type: GrantFiled: March 21, 2018Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
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Publication number: 20180219066Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.Type: ApplicationFiled: March 21, 2018Publication date: August 2, 2018Inventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
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Patent number: 9985097Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.Type: GrantFiled: June 30, 2016Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
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Publication number: 20180006113Abstract: A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Inventors: Kangguo Cheng, James J. Demarest, John G. Gaudiello, Juntao Li
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Patent number: 7932167Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.Type: GrantFiled: June 29, 2007Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, Steven J. Holmes, David V. Horak, Charles William Koburger, III, Chung Hon Lam
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Patent number: 7699996Abstract: A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD<W2<2D<W3.Type: GrantFiled: February 28, 2007Date of Patent: April 20, 2010Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, III
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Patent number: 7560692Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.Type: GrantFiled: December 28, 2006Date of Patent: July 14, 2009Assignees: International Business Machines Corporation, Dongbu Electronics Co., Ltd.Inventors: Keith E. Barton, Steven H. Boettcher, John G. Gaudiello, Leon J. Kimball, Yun-Yu Wang
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Publication number: 20090001337Abstract: A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.Type: ApplicationFiled: June 29, 2007Publication date: January 1, 2009Inventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, Steven J. Holmes, David V. Horak, Charles William Koburger, III, Chung Hon Lam
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Publication number: 20080206996Abstract: A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD<W2<2D<W3.Type: ApplicationFiled: February 28, 2007Publication date: August 28, 2008Inventors: Toshiharu Furukawa, John G. Gaudiello, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger
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Publication number: 20080156987Abstract: A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Keith E. Barton, Steven H. Boettcher, John G. Gaudiello, Leon J. Kimball, Yun Yu Wang