Patents by Inventor John G. Gierach
John G. Gierach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004833Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 10, 2023Publication date: January 4, 2024Applicant: Intel CorporationInventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
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Publication number: 20230410247Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 9, 2023Publication date: December 21, 2023Applicant: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
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Patent number: 11776195Abstract: Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.Type: GrantFiled: August 31, 2021Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: John G. Gierach, Karthik Vaidyanathan, Thomas F. Raoux
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Patent number: 11763415Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.Type: GrantFiled: September 24, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
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Patent number: 11748302Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 23, 2021Date of Patent: September 5, 2023Assignee: INTEL CORPORATIONInventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
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Patent number: 11715173Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.Type: GrantFiled: April 24, 2019Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
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Patent number: 11704856Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.Type: GrantFiled: November 18, 2021Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
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Publication number: 20220222884Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.Type: ApplicationFiled: November 18, 2021Publication date: July 14, 2022Applicant: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
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Publication number: 20220206990Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 23, 2021Publication date: June 30, 2022Applicant: Intel CorporationInventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
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Publication number: 20220068005Abstract: Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.Type: ApplicationFiled: August 31, 2021Publication date: March 3, 2022Inventors: John G. GIERACH, Karthik VAIDYANATHAN, Thomas F. RAOUX
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Publication number: 20220012843Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 24, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
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Patent number: 11210265Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.Type: GrantFiled: May 7, 2020Date of Patent: December 28, 2021Assignee: INTEL CORPORATIONInventors: Altug Koker, Prasoonkumar Surti, David Puffer, Subramaniam Maiyuran, Guei-Yuan Lueh, Abhishek R. Appu, Joydeep Ray, Balaji Vembu, Tomer Bar-On, Andrew T. Lauritzen, Hugues Labbe, John G. Gierach, Gabor Liktor
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Patent number: 11182948Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.Type: GrantFiled: December 18, 2020Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
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Patent number: 11182296Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.Type: GrantFiled: September 10, 2019Date of Patent: November 23, 2021Assignee: Intel CorporationInventors: Andrew T. Lauritzen, Gabor Liktor, Tomer Bar-On, Hugues Labbe, John G. Gierach, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Abhishek R. Appu, Balaji Vembu, Altug Koker
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Patent number: 11107263Abstract: Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.Type: GrantFiled: November 13, 2018Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: John G. Gierach, Karthik Vaidyanathan, Thomas F. Raoux
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Patent number: 11017494Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.Type: GrantFiled: July 23, 2020Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Kai Xiao, Ankur N. Shah, John G. Gierach
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Publication number: 20210150798Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.Type: ApplicationFiled: December 18, 2020Publication date: May 20, 2021Applicant: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
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Patent number: 10957095Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.Type: GrantFiled: August 6, 2018Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Karthik Vaidyanathan, Won-Jong Lee, Gabor Liktor, John G. Gierach, Pawel Majewski, Prasoonkumar Surti, Carsten Benthin, Sven Woop, Thomas Raoux
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Patent number: 10957096Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.Type: GrantFiled: June 20, 2019Date of Patent: March 23, 2021Assignee: hiel CorporationInventors: Hugues Labbe, Tomer Bar-On, Gabor Liktor, Andrew T. Lauritzen, John G. Gierach
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Patent number: 10957050Abstract: Systems, apparatuses and methods may provide for technology that partitions a three-dimensional (3D) scene into a plurality of layers including at least a foreground layer and a background layer. Additionally, the foreground layer may be rendered at a first rate and the background layer may be rendered at a second frame rate, wherein the first frame rate is greater than the second frame rate. In one example, the foreground layer and the background layer are composited into a frame.Type: GrantFiled: November 19, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Hugues Labbe, Tomer Bar-On, John G. Gierach, Gabor Liktor, Andrew T. Lauritzen